Abstract: A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory has a cache directory for recording main storage addresses mapped into cache memory, identifying cache lines as valid or invalid, and holding status bits of data words stored in the cache memory. According to the process, a data word is stored in the cache memory during a first clock cycle and the associated cache directory is read to determine whether the corresponding main storage address is mapped into the cache memory. If so, and if no status bits in the data word require update, the store to the cache memory is complete.

Abstract: An electronics system communicates among its subsystems by a free-space optical bus. The bus transmits signals bidirectionally along a single linear axis as polarized beams of light. Each subsystem has a bus interface unit for generating outgoing beams along both axial directions, and for receiving incoming beams from both axial directions. The interface units use laser generators, photodetectors, and amplitude beam splitters.

Abstract: A data processing network includes multiple processing devices, one or more memory cards in main storage, and a shared interface for processor access to main storage. Each of the memory cards includes dynamic random access memory arrays which require a periodic refresh pulse. To provide refresh pulses, each of the memory cards includes a programmable register, a counter receiving clock pulses, and a comparator. The comparator generates a request pulse each time the output from the pulse counter equals a selected value provided by the register. The register is programmable to controllably adjust the selected value, and thus select the frequency at which refresh request pulses are generated by the comparator. The memory card further includes a buffer for receiving the refresh request pulses and generating a refresh request responsive to each pulse.

Abstract: An enclosure for different subsystem variations of a data processing system has a box with front and rear regions separated by an interconnection carrier. The front is divided into standard-size bays for functional modules, while support modules slide into rear bays. A vertical central carrier contains electrical interconnections between the functional and support modules. An environmental module provides cooling air through the enclosure.

Abstract: A hardware data string operation controller is provided which (1) performs variable length main store string operation; (2) executes at least a subset of both left to right and right to left instructions, having variable length multibyte operands; and (3) performs multicycle storage to storage operations on variable length multibyte operand data, all under the control of a single control word. The controller comprises (a) means for dynamically determining (and if necessary, adjusting) the maximum number of operand related data string bytes that can be processed (by the controller) during each machine cycle (referred to as"data mode" calculation/alteration); (b) means for performing partial machine "holdoffs" (i.e.

Abstract: A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected location in the memory arrays and latched into the internal register. The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected location in the arrays.

Abstract: A fully redundant safety interlock system is provided comprising, means for detecting the loss of light on a fiber optic link; controller means, coupled to said means for detecting, for determining the safety condition of the link based on the output of said means for detecting, and for controlling the radiant energy output of an optical transmitter, based on the determined safety condition, via redundant output control signals; and means, coupled to said controller means, responsive to said redundant control signals, for interconnecting the output of said controller means to transmitter drive circuitry to thereby adjust the radiant energy output by the transmitter. According to a preferred embodiment of the invention, the controller means includes an electronic implementation of two independent state machines, each of which redundantly determines the connection state of the optical link between two optical link cards.

Abstract: A text document is stored as a sequence of primary records linked by a table. When an operator changes one of the records, the changed text is stored as a secondary record associated with a primary record in the table. If the operator later chooses to undo the changes, the secondary records are deleted. If he chooses to keep the changes, the secondary records are substituted for the associated primary records, and the latter are deleted.

Abstract: A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus for transmitting working information between the processors and memory cards. Auxiliary busses, including a command/address bus for commands and address information and a communication bus for status information, are connected to all of the processing devices and slave devices and operate in parallel with the working data bus. A system for distributing control of the working information bus, among all of the master devices and slave devices, includes a grant token and plural select tokens. The grant token, a line connected in common to all devices, permits a device currently controlling the interface to retain control until it completes its transmission.

Abstract: A digital system generates a single-phase master clock and distributes it to multiple cards and chips incorporating the functional logic of the system. A circuit in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.

Abstract: An electronics system communicates among its subsystems by a free-space optical bus. The bus transmits signals bidirectionally along a single linear axis as polarized beams of light. Each subsystem has a bus interface unit for generating outgoing beams along both axial directions, and for receiving incoming beams from both axial directions. The interface units use laser generators, photodetectors, and amplitude beam splitters.

Abstract: In connection with an information processing network in which multiple processing devices have individual cache memories and also share a main storage memory, a process is disclosed for allocating multiple data operations or tasks for subsequent execution by the processing devices. A plurality of task dispatching elements (TDE) forming a task dispatching queue are scanned in an order of descending priority, for either a specific affinity to a selected one of the processing devices, or a general affinity to all of the processing devices. TDEs with specific affinity are assigned immediately if the selected processor is available, while TDEs of general affinity are reserved. TDEs with a specific affinity are bypassed if the selected processor is not available, or reserved if a predetermined bypass threshold has been reached. Following the primary scan a secondary scan, in an order of ascending priority, assigns any reserved tasks to the processing devices still available, without regard to processor affinity.

Abstract: A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

Abstract: A redundant, fault-tolerant connection is provided from a local processing station to a plurality of remote processing stations, each including an I/O bus and an associated I/O bus interface logic circuit. Two of the bus interface logic circuits are connected directly to the processor interface circuit, via separate direct links. Intermediate bus interface circuits of and I/O busses of intermediate remote stations are connected between the two selected bus interface circuits, in a series arrangement including alternate link segments and bus interface circuits. Each of the bus interface circuits has pass-through capability for transmitting data in either direction, and the links and link sections also are bidirectional, enabling transmission of data in either direction and on either path between the processor interface circuit and any of the remote stations, through any intervening stations. The processor interface circuit itself is intentionally configured without such pass-through capability.

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.