Abstract: A method and apparatus for transferring data in parallel from a smaller to a larger register is described, in which the larger register comprises a first and a second set of master and slave latches with a one shot employed for clocking the master latches in the first set. In operation, a first word from the smaller register is latched into the first set of master latches in response to an output from the one shot which occurs on the trailing edge of a clock pulse applied to the larger register. On the leading edge of a subsequent clock pulse applied to the larger register, a second data word is latched in the second set of master latches. Immediately thereafter the first and the second set of slave latches are opened for transferring the first and second words at their inputs to their outputs in parallel. Following the transfer of the first and second words to the outputs of the first and second set of slave latches, the slave latches close, latching the first and second words.

Abstract: A line receiver circuit having an input hysteresis characteristic which is compensated for both temperature changes and variations in supply voltage includes a receiver circuit portion, a bandgap circuit portion, a first voltage divider network, a second voltage divider network, and a feedback switching transistor. The receiver circuit portion is responsive to an input logic signal for generating an output signal. The bandgap circuit portion generates a constant reference voltage. The first and second voltage divider networks are operatively connected to the constant reference voltage. The switching transistor is responsive to the output signal for switching between the first voltage divider network generating a high threshold voltage when the input logic signal is in the low level state and the second voltage divider network generating a low threshold voltage when the input logic signal is in the high level state.

Abstract: A logic gate circuit composed of CMOS transistors includes at least a first pair of transistors formed of first and second transistors of one conductivity type having gate, source and drain electrodes. The logic gate circuit further includes at least a second pair of transistors formed of third and fourth transistors of the same conductivity as the first pair and having gate, source and drain electrodes. The source and drain electrodes of the first and second pairs are adapted to receive input signals. A pair of cross-coupled transistors formed of fifth and sixth transistors of a complementary electrodes are provided. The gate of the fifth transistor is connected to the drain of the sixth transistor, and the gate of the sixth transistor is connected to the drain of the fifth transistor. The drain of the fifth transistor is further connected to the drains of the first and second transistors and to a true output terminal.

Abstract: A method and apparatus for reading data from a disk having missing or unreadable field address marks. Expected address marks are searched for within a time window which is generated using a counter. When an expected address mark is generated at any time within the time window, the counter is set or reset to generate another time window within which the next address mark is expected to occur. By starting or restarting the counter each time an expected address mark is detected the effects of variations in spindle speed which occur prior to the detection of the address mark are eliminated, thus increasing the probability that readable address marks will be detected within a time window.

Abstract: An improved lateral polysilicon diode in an integrated circuit structure is disclosed. The diode is characterized by low reverse current leakage, a breakdown voltage of at least 5 volts, and low series resistance permitting high current flow before being limited by saturation. The polysilicon diode comprises a polysilicon substrate having a first zone sufficiently doped to provide a first semiconductor type and a second zone sufficiently doped to provide a second semiconductor type whereby the junction between the two zones forms a diode. The lateral edges of the diode are treated to remove defects to thereby inhibit current leakage around the edges of the lateral diode to lower the reverse current leakage of the diode.

Abstract: A unitary multiplexer-decoder circuit integrated on a single semiconductor chip includes a first reference transistor, a plurality of first data input transistors, a second reference transistor, a plurality of second data input transistors, an emitter follower, a first current source and a second current source. A reference voltage generator is provided for generating first and second reference potentials and is formed on the same integrated circuit substrate as the multiplexer-decoder circuit.

Abstract: Logic circuits formed of merged P-channel MOS transistors and bipolar transistors to produce a single logic gate include a plurality of P-channel MOS transistors and a pair of bipolar transistors. The logic gate circuits have low power dissipation and a large noise margin.

Abstract: A semiconductor device having grooves of different depths for improved device isolation is presented. In the preferred embodiment of the present invention, a first groove and a second groove provide isolation of devices within regions of different conductivity type. The first and second grooves are each shallower than the conductivity type region in which they reside. A third groove is formed between adjacent regions of different conductivity type. The third groove is deeper than both the first groove and the second groove and extends to a depth sufficient to penetrate the substrate of the semiconductor device. The third groove operates to prevent latch-up between devices in the adjacent well regions. Filler materials are used to fill the first, second and third grooves to improve their respective isolating characteristics.

Abstract: Disclosed is a circuit providing a controllable effective resistance which comprises of transistor means that provides current at an input node responsive to an input voltage at the input node. The transistor means is coupled to a settable current source which operates to control the effective value of the controllable effective resistance. The invention also includes a filter which employs the controllable effective resistance to vary the breakpoint frequency of the filter. Also, a phase-locked loop apparatus employing the filter is disclosed.

Abstract: A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.

Abstract: An improved semiconductor memory device for serial scan applications is presented. The semiconductor memory device as presented includes a main memory means combined with an on-board means for implementing a shift register function. The shift register function of the present invention is implemented by utilizing a secondary memory means in conjunction with parallel loadable, multiple-bit address counters.

Abstract: A non-inverting high speed low level gate to Schottky transistor logic translator circuit includes a first input circuit adapted for receiving a first input signal and having its outputs connected to a first node and a second node. A first Schottky transistor is provided which has its base connected to the first node and to a voltage supply potential via a first resistor, its emitter connected to the second node and its collector connected to a third node and to the supply potential via a second resistor. A second Schottky transistor is provided which has its base coupled to the third node, its collector connected to the supply potential via a third resistor and its emitter connected to a fourth node. An upper output transistor has its base connected to the fourth node and to a ground potential via a fourth resistor, its collector connected to the supply potential via a fifth resistor and its emitter connected to an output circuit terminal.

Abstract: An improved method is disclosed for isolating active devices in an integrated circuit structure containing both CMOS and bipolar devices to simultaneously form isolation regions to separate CMOS channels from adjacent channels or bipolar devices as well as to separate adjacent bipolar devices from one another. The improved method of isolation also results in the simultaneous formation of a retrograde p-well for the n-channel device. The improved method comprises implanting, into a substrate having field oxide portions previously grown thereon, impurities capable of forming one or more isolation regions, between the active devices, at an energy level sufficiently high to permit penetration of the impurities through the field oxide.

Abstract: An improved method for forming a conductive path through at least one layer of insulating material in an integrated circuit structure comprising a narrow portion and a sloped oversized portion of the conductive path. The method comprises forming the sloped oversize portion of the conductive path by defining an opening in a layer of photoresist material applied over the layer of insulating material, sloping the edges of the photoresist layer adjacent the opening to define an angle with the plane of the underlying insulating layer, and etching the photoresist layer and the insulating layer with an etchant capable of removing both materials to form the sloped oversized portion of the conductive path. The narrow portion of the conductive path is formed by etching at least a portion of the insulating layer to expose a selected section of the integrated circuit structure below the insulating layer. Either the oversized sloped portion or the narrow portion may be formed first.

Abstract: A line driver circuit is formed of a driver circuit section and a receiver circuit section. The driver circuit section provide a low impedance drive for charging and discharging quickly a capacitive load. A receiver circuit section includes an output level-shifting transistor which is adapted for translating a voltage at an output node of the driver circuit section to a compatible higher level.

Abstract: A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.

Abstract: An improved integrated circuit structure, and method of making the structure, is disclosed wherein at least one metallization layer is coated with a conductive indium arsenide layer during production of the structure and an upper metallization layer subsequently is applied to the structure wherein at least a portion of the subsequent metallization layer is in ohmic contact with the conductive indium arsenide layer whereby the lower metallization layer is protected by the intervening indium arsenide layer during subsequent removal of the upper metallization layer if subsequent reworking of the structure becomes necessary. The use of the indium arsenide layer over a metallization layer further enhances the construction process by the use of its antireflective properties during patterning of a photoresist applied over the indium arsenide layer.

Abstract: Slots of different types are fabricated using a single latent image mask. The slots of different types are thus located with respect to each other in a self-aligned relationship. In one embodiment an oxide of the semiconductor material, e.g., silicon dioxide, is used as a unitary masking layer. The slots of various types are defined in the mask and are fabricated in succession by relying on a universal etch and differential thicknesses for the oxide layers over slots of the different types. When the slots are formed they are filled with a suitable material. In another embodiment at least a dual layer latent image mask is used in which the two materials have different etch properties. One layer is used as a stop etch layer during fabrication of one of the slot types.

Abstract: A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.

Abstract: An output voltage driver apparatus for an ECL circuit driving a capacitive load is disclosed which comprises an emitter follower means having an output emitter and a reference emitter. The output emitter is connected to the capacitive load. A pull-down transistor means is connected to the output emitter and provides a transient pull-down current for a capacitive load when the output voltage swings from a high level to a low level. A biasing means is connected between the reference emitter of the emitter follower means and the pull-down transistor means so that the pull-down transistor means is biased to turn on when the voltage at the output emitter is higher than the voltage at the reference emitter by a turn-on voltage.