Abstract: An elastic buffer includes a memory array for storing received data, each location within the array having an associated cell storing a flag indicative of the most-recently performed (i.e., read or write) on the associated memory location. A potential write overflow of the memory is detected whenever a write attampt is made to a location whose flag indicates a write was most-recently performed. A potential read underflow is detected whenever a read attempt is made to a location when the flag associated with the location next to be read indicates a read was most recently performed. Also, a potential write operation of a memory location prior to the completion of a read on the next location within the array are also generates an overflow/underflow condition. Metastable logic state conditions within the array are avoided because the potential overflow/underflow conditions take cognizance of the finite propogation and setting times of signals within the array.

Abstract: A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals.

Abstract: A full adder circuit includes a sum circuit section, a carry-out circuit section, a carry-in circuit section; and an output circuit section. The sum circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The sum circuit section also includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-out circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The carry-out circuit section also includes a plurality of N-channel MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order.

Abstract: A dynamic ECL line driver circuit for driving line loads having significant capacitance which includes an input transistor, a reference transistor, a main current source transistor and an emitter follower transistor. The line driver circuit further includes a dynamic current enhancement circuit formed of a buffer portion, a current enhancement portion and a dynamic charge pumping portion. The current enhancement portion includes a current source enhancement transistor and the dynamic charge pumping portion includes a capacitor. The buffer portion is utilized for amplifying and inverting a transient voltage at the collector of the reference transistor. One end of the capacitor is connected to the collector of the reference transistor and the base of the emitter follower transistor, and the other end thereof is coupled to the base of the current source enhancement transistor via the buffer portion.

Abstract: An improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: An improved bipolar device is disclosed having a polysilicon emitter formed over a base region of a silicon substrate with oxide spacer portions formed on the sides of the emitter and metal silicide portions formed over the base region adjacent the oxide spacers whereby the use of polysilicon for the emitter results in high gain as well as vertical shrinking of the device because of the shallow diffusion of the emitter into the base and the elimination of an extrinsic base region. The use of oxide spacers and metal silicide adjacent the spacers results in a shrinkage of the horizontal spacing of the device to lower the base-emitter resistance and capacitance to thereby increase the speed of the device.

Abstract: An improved thin film resistor material is disclosed which comprises a chromium-silicon-carbon material containing from about 25 to 35 wt. % chromium, about 45 to 55 wt. % silicon, and about 20 to 30 wt. % carbon. The resistor material is further characterized by a resistivity of greater than about 800 ohms per square to less than about 1200 ohms per square, a temperature coefficient of resistance of less than 160 ppm per degree Centigrade, and a lifetime stability of less than 0.1% change in resistivity. In the preferred embodiment, the resistor material contains 31 wt. % chromium, 46 wt. % silicon, and 24 wt. % carbon.

Abstract: Output buffer circuits formed of merged bipolar transistor and CMOS transistors to produce either two output states or three output states includes a plurality of CMOS transistors and a pair of bipolar transistors. The output buffer circuits have high current drive capabilities and low propagation delay.

Abstract: A logic level translator having a fast rising edge at its output for converting ECL logic levels into TTL logic levels includes a switching transistor having its base adapted to receive an input logic level signal representative of an ECL signal, the collector of the switching transistor being connected to an output node. A clamp delay circuit is interconnected between the collector and the base of the switching transistor for inhibiting the switching transistor from receiving feedback current to its base so as to cause a faster turn-off, thereby producing a fast rising edge response at the output node during a high-to-low transition of the input logic level signal.

Abstract: An improved dynamic random access memory (DRAM) cell circuit (46) having a charge amplifier is presented. The improvement comprises a bipolar amplification means (64) for amplifying a charge as it is read out of the memory cell (46). According to one embodiment of the present invention, in addition to a standard charge storage capacitor (50) and MOS transistor (48), the memory cell (46) also includes a write control line (60) and a second MOS transistor (62) for writing a "1" bit of information into the memory cell (46). These improvements require little or no additional space when used in a DRAM circuit and allow a reduction in the required capacitor area.

Abstract: Disclosed is an apparatus for synchronizing a first signal with a second signal comprising a plurality of delay means D.sub.i as i goes from 1 to N, where N is an integer, each delay means D.sub.i having an input I.sub.i and a delay output O.sub.i for delaying a signal received at the respective input I.sub.i by an increment .delta.t of time in supplying the delayed signal at the respective delay output O.sub.i. The first delay means D.sub.1 of the plurality of delay means is connected to receive the first signal at its input I.sub.1. Each of the other delay means D.sub.i, for i equal to 2 to N, are connected in series such that the respective input I.sub.i is connected to receive the delay output O.sub.i-1 of the preceding delay means D.sub.i-1. A plurality of latch means L.sub.i, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L.sub.i latches the signal at the delay output O.sub. i respectively for each of the delay means D.sub.

Abstract: A tri-level buffer circuit includes three phase splitter bipolar transistors. The buffer circuit consumes less power in the tri-state mode than in the low logic state by reducing the amount of current drawn through the tri-state control line. The buffer circuit incorporates a temperature-controlled current source which supplies a greater amount of current at a low temperature and supplies a smaller amount of current at a high temperature.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to coupled the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: A multilevel differential logic gate circuit for generating a plurality of levels of logic includes a single constant current source having its one end connected to a ground potential. The current source has a relatively small voltage drop. A first differential amplifier formed of a pair of first and second transistors have their emitters coupled together and to the other end of the current source to define a first level of logic. A second differential amplifier formed of a pair of third and fourth transistors have their emitters coupled together and to the collector of the first transistor to define a second level of logic. A third differential amplifier formed of a pair of fifth and sixth transistors have their emitters coupled together and to the collector of the third transistor to define a third level of logic.

Abstract: An improved method is provided for defining interconnect patterns in an integrated circuit fabricated on a semiconductor wafer. The improvement comprises the step of immersing the wafer in a weak base solution, prior to etching a titanium-tungsten barrier layer, so as to remove from the wafer chlorides and flourides remaining as a result of a previous step of etching a conductor layer. In a preferred embodiment of the invention, a step of immersing the wafer in a strong acid solution is also performed to remove chlorides from the wafer.

Abstract: The present invention discloses a low order charge-pump filter operable with a single variable current source. The integrating capacitor of the charge-pump is connected in an H-bridge switching configuration with four switches that are operable to control the current source to supply current to a first node of the capacitor or to a second node of the capacitor or to bypass a capacitor, depending on the state of operation of the charge-pump. The charge-pump filter disclosed is particularly useful for providing the low order response for a phase detector in a phase-locked loop.

Abstract: A method and apparatus for transferring data between a disk and a CPU is disclosed comprising a pair of toggling header buffers and a pair of toggling data buffers. In operation, data is transferred between a sector on a disk and one of the data buffers under the control of one of the header buffers. While the data in the header buffer is being transferred between the data buffer and a CPU, data is transferred between an adjacent sector on the disk and the other data buffer under the control of the other header buffer. The rate of transfer of data between the data buffer and the CPU is higher than the rate of transfer of the data between the disk and the other data buffer. This provides sufficient time to check the data transferred from and to the CPU for errors and to address a new sector on the disk prior to the completion of the data transfer of the previous sector between the disk and the data buffer.

Abstract: A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

Abstract: An improvement in the process of constructing an integrated circuit structure in which a photoresist layer is applied to an integrated circuit structure followed by plasma etching of the structure is disclosed which comprises exposing the photoresist material to light, preferably UV light, prior to the etching step whereby the surface of the structure beneath the photoresist will be smooth after the etching step and removal of the photoresist.

Abstract: An emitter coupled gate circuit for providing both a full output voltage swing and a fractional output voltage swing with an adjustable high level output voltage includes a single differential transistor circuit having a first current switch transistor and a second current switch transistor and a single constant-current source. A first load resistor has its one end connected operatively to the collector of the second current switch transistor. A second load resistor has its one end connected operatively to the collector of the second current switch transistor, and a level shifting resistor has its one end connected to the other end of the second load resistor. A first emitter follower transistor has its base connected to the one end of the first load resistor and its emitter connected to an upper-level full output voltage swing terminal.