Patents Represented by Attorney J. Vincent Tortolano
-
Patent number: 4720831Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.Type: GrantFiled: December 2, 1985Date of Patent: January 19, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Sunil P. Joshi, Venkatraman Iyer
-
Patent number: 4720830Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock.Type: GrantFiled: December 2, 1985Date of Patent: January 19, 1988Assignee: Advanced Micro Devices, Inc.Inventors: Sunil P. Joshi, Venkatraman Iyer
-
Patent number: 4719366Abstract: A D-type master-slave flip-flop includes a master section, a slave section and an output state protection network. The master section has a data input node and a clock input node. The slave section has at least one data output node connected to an output terminal. The output state protection network is responsive to the master section for toggling the slave section so that the data output node is returned to its initial logic state when the output terminal is free of transient noise.Type: GrantFiled: October 11, 1985Date of Patent: January 12, 1988Assignee: Advanced Micro Devices, Inc.Inventor: Sherman M. Tan
-
Patent number: 4719593Abstract: A programmable event generator for generating digital timing waveforms in response to a triggering signal includes one programmable read-only memory for storing and outputting data words corresponding to the digital timing waveforms and next address words to address another of the data words, a storage register for temporarily storing and outputting any one of the data words and next address words, another mapping programmable read-only memory for storing and outputting starting address words to start the addressing of the one programmable read only memory, a multiplexer to select either a starting address word or a next address word to address the one programmable read-only memory, and a programmable control circuit, responsive to the triggering signal, for clocking the storage register at a programmed clock frequency.Type: GrantFiled: July 9, 1984Date of Patent: January 12, 1988Assignee: Advanced Micro Devices, Inc.Inventors: N. Bruce Threewitt, Jimmy R. Madewell
-
Patent number: 4719565Abstract: A single-chip microprogram sequence controller can be selectively operated in either an interrupt mode or a trapped mode. In the interrupt mode, the miroprogram sequencer allows the currently-executing microinstruction to finish execution before beginning the interrupt routine which services the asynchronous event which requested the interruption of the presently-executing microinstruction stream. In the trap mode, the sequencer aborts the currently-executing microinstruction to avoid an irreversible error which would result if the microinstruction were to finish execution before beginning the routine which services the event which requested trapping of the presently-executing microinstruction.Type: GrantFiled: November 1, 1984Date of Patent: January 12, 1988Assignee: Advanced Micro Devices, Inc.Inventor: Ole H. Moller
-
Patent number: 4717914Abstract: Methods are disclosed for operating receiver devices which take serial data patterns off a high speed synchronous serial transmission media and covert the data to parallel pattern outputs. According to the invention, each device operates under a "permission to capture" data protocol which allows a given receiver to operate at the byte rate of the transmitted data. Devices using the disclosed methods may be operated individually or in a cascaded fashion, In either mode, by enabling the receivers to transfer high speed data at the transmitted pattern byte rate, as opposed to the bit rate, the reliability and capacity of the receivers to field high speed data is enhanced. In addition, the disclosed methods obviate the need for receivers operating in a cascade mode to "know" their position in a cascade chain. As a result the operating simplicity and reliability of devices that employ the disclosed methods is further enhanced.Type: GrantFiled: December 18, 1985Date of Patent: January 5, 1988Assignee: Advanced Micro Devices, Inc.Inventor: Paul H. Scott
-
Patent number: 4716381Abstract: An operational amplifier suitable for inclusion in an integrated circuit device operating as a transceiver at a coaxial media interface to a network meeting IEEE 802.3 standards. To be included in an integrated circuit package the operational amplifier must have low-power consumption and yet generate up to 80 mA of current onto the network. A design method achieves this goal, producing an operational amplifier having three independently-positioned, isolated, poles. A current generator and level shifter is employed with the operational amplifier which generates a current precisely proportional to a "collision" reference voltage, the current is compensated for changes in temperature and for variations in transistor gain (hFE). A very wide band level shifter matches the current generated to the requirements of the operational amplifier so that 10% to 90% changes in current generated by the op amp can occur in 1/2 to 3/4 of a nanosecond, yet the level shifter does not consume much power.Type: GrantFiled: April 3, 1986Date of Patent: December 29, 1987Assignee: Advanced Micro Devices, Inc.Inventor: David L. Campbell
-
Patent number: 4716467Abstract: A method and device for speeding the transmission and reception of documents by digital facsimile systems employing two-dimensional coding. Information regarding a reference line of a document need not be reaccessed from memory during the processing of the scan line next-following a uni-color reference line. A user-accessible paper-width register utilized in conjunction with a comparator according to the speed-up method permits ready detection of uni-color lines and permits encoding and decoding according to either of two international standards. Utilization of the paper-width register affords ready availability of the accumulated run-length of picture elements within uni-color lines without the need to accumulate the run length or reaccess the uni-color reference line.Type: GrantFiled: February 27, 1985Date of Patent: December 29, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Vinod Menon, Shinkyo Kaku
-
Patent number: 4714877Abstract: A three-voltage level detector include an input terminal for receiving an input logic signal having either a high level, mid-level or low level voltage. A first level sensing buffer is responsive to the input logic signal for generating a first output sense voltage indicative of whether the input logic signal is either at the (a) high level voltage or (b) mid-level or low level voltage. A second level sensing buffer is responsive to the input logic signal for generating a second output sense voltage indicative of whether the input logic signal is either at the (a) high level or mid-level voltage or (b) low level voltage.Type: GrantFiled: December 2, 1985Date of Patent: December 22, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Samuel K. Kong
-
Patent number: 4714520Abstract: A process is disclosed for filling a trench in an integrated circuit structure without forming a void in the trench which, in a preferred embodiment, comprises partially filling the trench with an etchable material, etching the material in the trench with an etchant capable of removing material adjacent the top of the trench at a rate faster than the rate of removal adjacent the bottom of the trench, and then filling the remainder of the trench with the material; whereby the material deposited adjacent the top of the trench will not close off the trench prior to complete filling of the bottom of the trench with the material.Type: GrantFiled: July 25, 1985Date of Patent: December 22, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Peter S. Gwozdz
-
Patent number: 4713605Abstract: An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.Type: GrantFiled: May 17, 1984Date of Patent: December 15, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Venkatraman Iyer, Gil S. Lee
-
Patent number: 4712215Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus used 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.Type: GrantFiled: December 2, 1985Date of Patent: December 8, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Sunil P. Joshi, Venkatraman Iyer
-
Patent number: 4710922Abstract: Apparatus and associated methods are disclosed for converting serial data pattern signals, transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel data pattern output signals. The disclosed devices are modular, may each be packaged as a single semiconductor integrated circuit device and are cascadable. When cascaded, the devices are capable of generating parallel data pattern output signals to one or more data sinks from a single serial bit stream.Type: GrantFiled: December 18, 1985Date of Patent: December 1, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Paul H. Scott
-
Patent number: 4710943Abstract: A daisy chain collision detection circuit for use with a StarLAN coded data transceiver includes a voltage comparator having an inverting input, a non-inverting input and an output. The inverting input of the voltage comparator is responsive to differential output voltages from a differential line drive and transient spike voltages from the primary of an isolation transformer. A charging capacitor is connected to the non-inverting input of the voltage comparator. The capacitor is charged to a reference voltage which is directly proportional to the peak voltage of the differential output voltages. The output of the voltage comparator provides an internal collision detection signal which is switched from a high logic level to a low logic level upon the occurrence of a daisy chain collision.Type: GrantFiled: December 12, 1986Date of Patent: December 1, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Raymond S. Duley, Leslie Forth
-
Patent number: 4706266Abstract: A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.Type: GrantFiled: November 5, 1986Date of Patent: November 10, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Asif Qayyum
-
Patent number: 4703486Abstract: A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.Type: GrantFiled: December 18, 1984Date of Patent: October 27, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Gerald L. Bemis
-
Patent number: 4703495Abstract: An improved, high-speed frequency divider circuit (32) is presented. The frequency divider circuit (32) is comprised of three D-type flip-flops (34, 36 38). The three flip-flops (34, 36, 38) are clocked synchronously for higher speed of operation. The design of the frequency divider circuit (32) embodies a sagacious state assignment to minimize the number of bits that change state on any given state transition, thus reducing the possibility of faulty circuit operation.Type: GrantFiled: May 23, 1986Date of Patent: October 27, 1987Assignee: Advanced Micro Device, Inc.Inventor: Bradley J. Bereznak
-
Patent number: 4698831Abstract: An incrementer cell includes an input section, an output section and a carry section. The input section is responsive to an input data signal and an input carry signal for generating an incremented output signal. The output section is coupled to the input section for generating a data out signal to be either the incremented output signal or the input data signal. The carry section is responsive to the input data signal and the input carry signal for generating a carry-out signal.Type: GrantFiled: June 20, 1986Date of Patent: October 6, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Yousef Vazir-Zadeh
-
Patent number: 4698523Abstract: There is disclosed herein a servo data demodulator for use in magnetic head positioning servo system for disk drives. The demodulator is comprised of a single peak detector which detects the maximum amplitude of the peaks in an input signal during specific times. A storage capacitor is used in the peak detector to store the peak level. This peak level is sampled a predetermined number of times during each data frame. Each sample is taken by a different sample and hold circuit, and the sequence of the samples is controlled by a timing generator. The capacitor of the peak detector is discharged by a switch controlled by the timing generator after each sample and before the next sample. The time delay before the first sample from the start of the frame and the sample time in the sequence is programmable by the user by setting certain inputs into the timing generator.Type: GrantFiled: November 1, 1985Date of Patent: October 6, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Eugen Gershon, Rudolph J. Sterner
-
Patent number: 4692888Abstract: An apparatus is described for summing the products of a predetermined number of successive pairs of numbers. In the apparatus there is provided an arithmetic unit having a first and a second input and an output, a first, a second and a third register and a first and a second multiplexer. In operation, a first pair of numbers are multiplied and the product thereof stored in the third register. Thereafter, a second pair of numbers are multiplied and the product thereof stored in the second register. Thereafter, the contents of the second and third register are added and the sum thereof stored in the third register. After the sum of the products of the first and second pairs of numbers are stored in the third register, the products of succeeding pairs of numbers are stored in the second register.Type: GrantFiled: October 3, 1984Date of Patent: September 8, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Bernard J. New