Abstract: The present invention provides a method and a circuit for increasing a time delay in an optical signal in an integrated optoelectronic circuit without a proportionate increase in the circuit area. The method uses multiple layers of optical waveguide fabricated in a vertical hierarchy in combination with concentric circular paths. The different sections of the optical waveguide delay line 103, 107 on the multiple layers are connected by electro-optic couplers to pass the optical signal between the sections. In a preferred embodiment, the optical couplers 105, 108 are a poled Electro-Optic (EO) region of cladding 506 allowing the coupler to be electrically addressed. Alternatively, in another embodiment, the couplers 105, 108 may be fabricated with a polymer that is optically nonlinear 406. This type of coupler could be addressed, or activated, by an optical signal, or a component of the optical signal traveling through the coupler.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--Al--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto, including a ground terminal (GND) and terminals for first and second supply voltages (VCC3, VCC5). A first inverter (5526) is connected between first supply voltage (3.3v) and ground and has a first inverter input (IN) and a first inverter output. A second inverter (5518) is connected between second supply voltage (5v) and ground and has a second inverter input (INT) and a second inverter output (OUT). A first feedback transistor (5520) has connections to the second supply voltage (5v), and to the second inverter input (INT) and the second inverter output (OUT). A second feedback transistor (5524) has connections to ground, and to the second inverter input (INT) and the second inverter output (OUT). First and second open-type inverters (5522, 5528) are connected to ground and each of the open-type inverters has an input and output.

Abstract: A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value corresponding to the destination of a branching instruction, and an associated register value, such as a stack pointer. Upon the execution of a subroutine call, the return address and current stack pointer value are stored in the return address stack, to allow for fetching and speculative execution of the sequential instructions following the call in the calling program. Any branching instruction, such as the call, return, or conditional branch, will have an entry included in the branch target buffer; upon fetch of the branch on later passes, speculative execution from the target address can begin using the stack pointer value stored speculatively in the branch target buffer in association with the target address.

Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934), first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (906), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an interface between the notebook computer and the docking station to transfer DMA station. Other devices, systems and methods are also disclosed.

Abstract: A focal plane array (30) for a thermal imaging system (20). The focal plane array (30) may include a number of thermal sensitive elements (42) bounded by a border (41). The thermal sensors (40) may provide a sensor signal output representative of the thermal radiation incident to the focal plane array (30). A multi-layer common electrode (36) may be coupled to the thermal sensitive elements (42) and the border (41). An optical coating (34) sensitive to infrared radiation may be provided in communication with the common electrode (36).

Abstract: A microcomputer integrated circuit (102) has a central processing unit (CPU) (702) first power management circuit (708) responsive to a system management interrupt (SMI) input for controlling operations of the CPU (702). A card interface integrated circuit (112) is adapted for coupling a card (24) to the microcomputer integrated circuit (102) and has a second power management circuit logic (1620, 1630) that responds to a plurality of interrupt event inputs (in CSC REGs A, B) and concentrates these inputs to a single card system management interrupt output (CRDSMI#). A peripheral processor integrated circuit (110) has a third power management circuit (920) including a plurality of system management interrupt (SMI) sources, and a SMI unit (2370). The SMI unit (2370) has an output (SMI#) connected to the SMI input of the microprocessor integrated circuit. The SMI unit (2370) responds to the card SMI output of the card interface integrated circuit (112) as well as the plurality of SMI sources.

Abstract: An illumination system (10) for exposing a xerographic printing apparatus (12). The system (10) includes a DMD-type imaging spatial light modulator (46), and a DMD-type optical switch (26) for modulating the intensity of the source light (15) irradiating the imaging DMD (46). A single conventional continuous wave tungsten lamp (14) is implemented with its light energy directed by a condensing lens (20) onto the DMD optical switch (26). The DMD optical switch (26) modulates the incident light (15), and passes reflected light to a light integrator (38), which in turn homogenizes and increases the aspect ratio of the light. The light integrator (38) directs the homogenized light via an anamorphic lens (40) onto the imaging DMD (46). The light energy provided to the imaging DMD (46) is precisely modulated in intensity, while remaining uniformly disbursed. The combination incandescent lamp (14) and optical DMD switch (26) offers a low cost, high-intensity alternative to LED arrays.

Abstract: An audio data processing system having a control processor coupled to an execution controller through a bus is provided. The control processor serves as a master processor to control the operation of the execution controller which in turn controls the execution of a multiplier accumulator. An ancillary data handler is provided to retrieve ancillary data from an input first in/first out (FIFO) buffer. Audio data is retrieved from the input buffer by the control processor and processed data is output through an output block.

Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.

Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

Abstract: A method for calibrating a printing system using a spatial light modulator. The spatial light modulator is an array of individually activated elements, all of which are set in a predetermined state, such as the ON state. Light is then directed onto the array and the resultant light passed into the printing system from the modulator is monitored by a sensor. Discrepancies between the light expected and received at the sensor are used to adjust the operation of the modulator to compensate for stuck or non-responsive pixels.

Abstract: A transponder unit (10) includes an N cycle counter (30) and an M cycle counter (28). The N cycle counter (30) has a different cycle value than the M cycle counter (28). During the transmission of information from the transponder unit (10), the duration for data bits having a binary zero value is controlled by the N cycle counter (30). The duration of data bits having a binary one value is controlled by the M cycle counter (28). The use of different cycle values within the N cycle counter (30) and the M cycle counter (28) allows for the transmission of binary one and binary zero data bits having the same bit length despite different frequencies representing the binary one and binary zero bits respectively.

Abstract: This is a locking system for a computing device. The system may comprise: a processor connected to a system bus; an input connected to the processor by the system bus; an output connected to the processor by the system bus; and a module that inserts into the computing device and is connected to the system bus; and a locking mechanism that locks and releases the module to and from the computing device. The locking mechanism may include: a primary lever which engages the module; a manual button which moves the primary lever and disengages the primary lever from the module; a pin that moves from a blocking position in front of the manual button to a non-blocking position clear of the manual button; and a solenoid that controls movement of the pin. Other devices, systems and methods are also disclosed.

Abstract: A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter.

Abstract: A virtual field programmable gate array device (20) includes a plurality of processors (22), each containing a central processing unit (24), memory (34), and a network interface (26). Each processor (22) may be programmed to emulate a multiple number of gates of a conventional field programmable gate array device. Each processor (22) is part of a network array to allow for information transfer between and among each processor (22). Information transfer is accomplished through the use of delivery units (50) that identify the routing vector for the information to an appropriate processor (22).

Abstract: An electronic switch (80) having a transistor (T) and a diode (D) formed on a substrate (82) is provided. The electronic switch (80) includes a common transistor collector and diode cathode region (81) of a first conductivity type formed in the substrate (82). The switch (80) also includes a transistor base region (83) of a second conductivity type formed in a first section of the collector region (81) and a transistor emitter region (84) of the first conductivity type formed in a section of the base region (83). Additionally, the electronic switch (80) includes a diode anode region (85) formed of the second conductivity type and in a second section of the collector region (81). At least a portion of the anode region (85) is selectively doped with a metallic dopant to provide centers for charge carrier recombination so as to decrease the recovery time of the diode (D).

Abstract: A TAB device (10) is coupled to a circuit board (12). The TAB device (10) includes a semiconductor die (11) having leads (18) extending therefrom. A material layer (30), typically a polyimide layer, covers the inward portion of the leads (18) to maintain leading position during attachment of the TAB device (10) to the circuit board (12). Prior to attachment, a backside encapsulation region (40) is applied to the backside of the TAB device (10), sealing the backside of the leads (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (18). The backside encapsulation material is selected to have a coefficient of thermal expansion similar to the coefficient of thermal expansion of the first material layer (30), to prevent excessive warpage.

Abstract: A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a second voltage level. After data has been read from the memory (10), the first group of bit lines (22) is discharged to the second voltage level.

Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.