Abstract: A method is disclosed for making a non-metallurgical connection between an integrated circuit (16) and either a circuit board (12) or second integrated circuit. In one embodiment, an electrical connection is formed between terminals (28) of an integrated circuit (16) and pads (20) on a circuit board (12) without metallurgically connecting the terminals (28) and pads (20). The integrated circuit (16) can be in either packaged or die form. A clamping mechanism (18, 36) attached to the circuit board (12) clamps the integrated circuit (16) to the circuit board (12).
Abstract: A computer system (6,7) includes first and second I/O circuits (932, 934), 51, 97 first and second buses (904, 83) respectively coupled to the first and second I/O circuits (932, 934), 51, 97 a memory (106), a third bus (104) coupled to the memory (106), and first and second bus interface circuits (902, 6920) connected between the third bus (104) and the first and second buses (904, 83) respectively. A direct memory access (DMA) controller (910) is coupled to the first bus (904) and to the first bus interface circuit (902), and a serial communications circuit (7010, 6910, 7020) is connected between the DMA controller (910) and the second bus interface circuit (6920). As an example, in the present invention a single DMA controller may be used to provide DMA capability to both a notebook computer and a docking station, using an related information between the DMA controller and a requesting device in the docking station. Other devices, systems and methods are also disclosed.
December 22, 1994
Date of Patent:
November 10, 1998
Texas Instruments Incorporated
James J. Walsh, Joseph Joe, Robert W. Milhaupt, James Bridgwater, Kazumi Haijima
Abstract: A method for setting the state of a clock-driven pseudo-noise sequence generator ("PNSG") having N stages, after the clock has been inhibited for a predetermined number K of clock cycles, to the state S.sub.2 (D) the PNSG would have been had the clock not been inhibited, based on the state S.sub.1 (D) the PNSG is in at the time inhibition of the clock is commenced. The method involves performing the following steps. First, a previously determined value, a(D)=the remainder of D.sup.Kq /f(D), is stored, wherein D is the delay transform operator, q=2.sup.N -2, and f(D)=c.sub.1 D.sup.N +c.sub.2 D.sup.N-1 + . . . +c.sub.N D+1. The product S.sub.2 (D)=a(D)S.sub.1 (D) is formed, wherein S.sub.1 (D)=s.sub.11 D.sup.N-1 +s.sub.12 D.sup.N-2 + . . . +s.sub.1N D.sup.0. If the degree of S.sub.2 (D) does not exceed N-1, the state bit values for S.sub.2 (D) are inferred from the product. However, if the degree of S.sub.2 (D) exceeds N-1, the product S.sub.2 (D) is first reduced by f(D), and then the state bit values for S.
Abstract: A method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory (10). The method comprises precharging a first group of bitlines (22) to a first voltage level. Other bit lines (22) are maintained at a second voltage level. After data has been read from the memory (10), the first group of bit lines (22) is discharged to the second voltage level.
Abstract: In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (V.sub.DD) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a conditional series discharge path (22, 24, and 16) connected to the precharge node and operable to couple the precharge node to a voltage different than the precharge voltage. The conditional series discharge path includes a low threshold voltage transistor (22 or 24) having a first threshold voltage, and a high threshold voltage transistor (16) having a second threshold voltage higher in magnitude than the first threshold voltage, wherein a voltage connected to a gate of the high threshold voltage transistor is disabling during the precharge phase.
Abstract: This invention relates to an improved LAN adapter. The LAN adapter includes a time division multiplex (TDM) ported RAM. The RAM is used to provide both network data FIFOs and control data storage in a single memory element. The network and peripheral components are able to access the same memory, but at different times in the cycle, thereby minimizing the component count and optimizing the operation of the adapter.
Abstract: A spherical illuminator (10, 40, 50, 60) having an upper diffuser (17, 47, 56, 62) with a concave surface, and having either an opposing reflector (18, 41) or an opposing lower diffuser (57, 63) with a concave surface. The two concave surfaces are placed so that their concavities form a substantially spherical viewing area into which the object under inspection is placed. The upper diffuser (10, 40, 50, 60) has a viewing aperture. It transmits light uniformly to the object from approximately two-pi steradians. The reflector (18, 41) or the lower diffuser (57, 63) provides light to the object in another two-pi steradians, resulting in nearly four-pi steradians of illumination.
Abstract: A low profile and light weight keyboard for portable electronic devices, such as notebook computers having a dual scissor movement. In one embodiment, the movement comprises an inner 318 and outer member 333, which connect at four pivot points. The two scissors appear as adjacent portions of the inner and outer members which are connected at a pivot point 308, and connected to each other with "living hinges." 310 The inner and outer movement members are attached or bonded to the keycap 302 and base 312 with the living hinge 310.
Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.
Abstract: A microprocessor (26) may multi-task a plurality of programs, and those programs include a virtual program (38 or 40) operable in a virtual mode and a monitor program (34) operable using protected mode semantics. The microprocessor includes input circuitry (INTR) for receiving an external interrupt request signal corresponding to an external interrupt directed to the virtual program, and additional input circuitry (INT#0-7) for receiving an external interrupt number corresponding to the external interrupt directed to the virtual program. The microprocessor further includes an interrupt handling circuit (30) comprising circuitry for identifying an interrupt vector and presenting an interrupt corresponding to the external interrupt request number. Lastly, the microprocessor includes control circuitry (28) coupled to the interrupt handling circuit.
March 25, 1997
Date of Patent:
October 20, 1998
Texas Instruments Incorporated
James E. Brooks, Robert R. Collins, Jonathan H. Shiell
Abstract: A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.
Abstract: This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.
Abstract: A system for transmitting data, comprising an interrogator (14) for transmitting an interrogation signal, a plurality of data collectors (12) for collecting data, a plurality of transponders (11) each coupled to a corresponding data collector (12) and each operable to receive the interrogation signal and to use the energy of the interrogation signal to transmit a response signal containing data from the data collector (12) associated with the transponder and wherein the interrogator (14) is further operable to receive the response signal from the transponders (11).
Abstract: An undersampling digital testability circuit 20 includes a bus 15, a data capture array 22 and a divider circuit 18. Divider circuit 18 provides an enablement signal to data capture array 22 that undersamples data travelling along the bus 15 at high data rates thereby effectively testing the integrity of high data rate transfers without the disadvantages of prior art test methodologies.
Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.
Abstract: The present invention provides a method of ameliorating the effects of misalignment between modulator, and a system using the same. The individual modulator elements are positioned such that a portion of the image produced is generated by both elements. The contribution to the combined output made by each element varies across the overlapped region, with each element making a small contribution to the pixels in the overlapped region at one end and a large contribution to pixels in the overlapped region at the other end. Because the overlapping output regions of the modulators collectively form a portion of the image, any alignment error is effectively spread over the entire overlapped region and is much less noticeable.
Abstract: A method of testing a large integrated circuit (10) of modular design. Test equipment is connected to a dedicated testing pad section (20) for each circuit section (22, 24, 34) of each module (12, 14, 16). The circuit section under test is tested via the testing pad adjacent that circuit section. The test equipment is then stepped to the testing section for the next circuit section. When testing is completed, the testing section is then electrically isolated from the circuit sections to prevent interference with operation of the entire circuit (10).
September 20, 1996
Date of Patent:
October 20, 1998
Texas Instruments Incorporated
Rohit L. Bhuva, Bao Tran, James L. Conner, Michael Overlaur, Tracy S. Paulsen
Abstract: A microprocessor (5) having a floating-point unit (31) with internal microcode control therein is disclosed. The microcode control is effected by a microsequencer (47) having a microcode ROM (68) and control circuitry (80) therein. A scheduler circuit (50) forwards status and condition information, such as results from floating-point operations received on buses (REG, RES, FS, X1) from elsewhere in the microprocessor (5), to a condition circuit (76; 76') in the microsequencer (47). The condition circuit (76; 76') includes a multiplexer (80) receiving each of the status values (STAT0 through STATn), along with a loop counter (81) and a programmable comparator (82). Microinstructions (.mu.
Abstract: In a preferred logic circuit embodiment (164), there is a signal path and a high threshold voltage transistor (46b) having a first threshold voltage and coupled to the signal path. The logic circuit further includes a precharge node (36) coupled to the signal path. The precharge node is to be precharged to a precharge voltage (V.sub.DD) during a precharge phase and operable to be discharged during an evaluate phase. The logic circuit also includes a conditional series discharge path (166) connected to the precharge node and operable to couple the precharge node to a voltage (ground) different than the precharge voltage. The conditional series discharge path includes two low threshold voltage transistors (168 and 170), each having a threshold voltage lower in magnitude than the first threshold voltage. Moreover, each low threshold voltage transistor receives a voltage connected to its gate where that voltage is disabling during the precharge phase.
Abstract: A computer system has an integrated circuit including a single-chip integrated circuit including an external-to-internal bus interface circuit coupled to external pins for connection to an external bus, and an on-chip internal bus coupled to the external-to-internal bus interface circuit and having a plurality of at-least-sixteen bit data paths including first and second such data paths. A parallel port on-chip is coupled to the on-chip internal bus and to both the first and second data paths therein. An interface circuit is coupled between the first and second data paths, wherein the first data path is connected to reflect the state of external inputs to the on-chip internal bus and of any internally generated second data path outputs to be sent externally, and wherein when the second data path carries internally generated signals to internal destinations, the states of the first and second data paths differ. Other circuits, systems and methods are also disclosed.