Abstract: The present invention provides a method for transferring groups of data between a microprocessor cache memory (114) and an external memory (105) across a data bus (Bbus). Each group of data includes as many bits of data as the width of the bus (Bubs) with the total amount of data transferred filling a line in the cache memory (114). The bus interface unit (112) of the microprocessor (110) initiates a burst read by starting a read request, asserting the address strobe bit and sending the initial requested address on the external bus address bits of the microprocessor (110). The external system will then respond by asserting a burst ready signal, followed by the data bits residing in the appropriate address position. The particular addresses for this data is selected according to the current burst mode, which may be high performance, low power or compatible with a previously known burst mode.

Abstract: A micromechanical optical switch (30). A reflective surface with two angled reflective surfaces (32,34) positioned opposite a micromechanical device (12). The micromechanical device is positioned such that light input along a path (36) to a first (32) of the two angled reflective surfaces is reflected to the micromechanical device. The micromechanical device then reflects the light to the second (34) of the angled surfaces to be output along another path (38a, 38b). The path (38a, 38b) that the second angled surface (34) outputs the light along is selected depending upon the position of the micromechanical device's reflective member (14). The reflective member (14) deflects from at least one hinge (22) to one of several positions. The number of positions available to the reflective member (14) depends upon the voltage applied to the electrodes (27a, 27b, 27c, 27d). The reflective member (14) makes no contact with any other surfaces, and thereby always returns to a know position upon loss of power.

Abstract: This invention has enabled a new, simple nanoporous dielectric fabrication method. In general, this invention uses a polyol, such as glycerol, as a solvent. This new method allows both bulk and thin film aerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Prior art aerogels have required at least one of these steps to prevent substantial pore collapse during drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although not required to prevent substantial densification, this new method does not exclude the use of supercritical drying or surface modification steps prior to drying. In general, this new method is compatible with most prior art aerogel techniques. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying.

Abstract: A system and method in which a transponder (14) is operable to transmit an original user account balance to an interrogator (12), which in turn calculates a revised user account balance and transmits the revised user account balance to the transponder (14). In one embodiment of the invention, the transponder (14) is further operable to transmit a verification user account balance back to the interrogator (12), which then compares verification user account balance to the revised user account balance that was earlier calculated and stored in an interrogator memory.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A device for replicating input/output protocols (265, 290, 310, 340, 360) in an expansion unit configuration (20, 60) implemented in a semiconductor chip (85) that supports a the protocols including one or more pass-through signal pathways (265), at least one serial protocol (310), at least one parallel logic protocol (340), and a peripheral component interface target device protocol (290). The device (85) may also support a dedicated data bus protocol (360) such as an 8-bit or 16-bit port and provides an interface pathway between various types of expansion units (20, 60) and a portable computer system (15) using the peripheral component interface bus (22) on the portable computer (15) as an interface between the system processor (17) and stand-alone peripheral devices (35, 110, 115, 117, 120, 125).

Abstract: A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An electronic device having addressable storage elements and a bus so that the storage elements are accessible via the bus, an address register connected to the bus, a data register connected to the bus, terminals for serial scan-in and scan-out, a scanable emulation control register coupled to the terminals, and a selecting circuit responsive to bits in the emulation control register for coupling the address register and the data register to the terminals to enable scanning of the address and data registers.

Abstract: A method and circuitry for testing a memory to determine its column address organization are disclosed. The disclosed circuitry is provided within a memory controller unit of a microprocessor unit, and includes a controllable multiplexer that selects certain combinations of address bits for use as column address bits to be applied to the memory; the selection of the multiplexer is controlled by the contents of a memory array type register associated with the memory or memory bank. In operation, a first data word is written to memory using a first address, and a second data word is written to memory using a second address that is spaced apart from the first address by a specified increment related to a trial number of column address bits of the memory.

Abstract: A system and method for transmitting data within a computer system is disclosed. The computer system includes a computer (12), a host device (14), a satellite device (16) and an interface (18). The interface (18) comprises a single conductor (28) which permits bi-directional communication between the host device (14) and the satellite device (16).

Abstract: A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit.

Abstract: The reliability of thin film insulators is determined with noise measurements which find the barrier height mean and standard deviation. A constant voltage source is applied across the thin film insulator. A low noise amplifier is connected across a resistor which is in series with the insulator. A spectrum analyzer is connected to the low noise amplifier. The power density is obtained by observing the output of a spectrum analyzer. The current spectral density is compared to a predetermined reference to detect the presence of defects in the insulator.

Abstract: A method and apparatus are disclosed for stressing the oxide layer (36) of an MOS integrated circuit during the fabrication process. One aspect of the invention is a method for fabricating an MOS integrated circuit. In accordance with this method, an oxide layer (36) is formed on a semiconductor substrate (34), and a gate layer (38) is formed on top of the oxide layer (36). During fabrication of the MOS integrated circuit, a potential is applied between the gate layer (38) and the semiconductor substrate (34) in order to stress the oxide layer (36). Other aspects of the invention include applying both a forward and reverse potential to stress the oxide layer (36). Also, the oxide stress can be applied at an elevated temperature. Elevated temperature aids in stressing the oxide layer (36).

Abstract: Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction.

Abstract: Variations on the Koehler illumination system, used for providing light to be reflected from, or transmitted by, an SLM. An anamorphic illumination system (10) uses multiple light sources (11) and a cylindrical lens (14) to provide an elongated and compressed beam to the SLM (16). A cascaded illumination system (30) uses multiple light sources (31) and multiple TIR prisms (33) to provide an extended light beam or one that is more intense, to the SLM (36).

Abstract: A microprocessor (5) including a clock domain translation circuit (50a) for communicating a digital signal from a high speed clock domain to a low speed clock domain is disclosed. The disclosed microprocessor (5) includes clock generation circuitry (20) which generates internal and bus clocks at different multiples of a system clock signal. The clock generation circuitry (20) includes a counter (60) that indicates, for a given frequency ratio, signals (REGION) indicating the current phase region of the faster clock (PCLK) relative to the slower clock (BCLK). The clock domain translation circuit (50a) includes a series of input registers (82, 84) in sequence, with the output of each as well as the input signal line (IN PCLK) coupled to inputs of a multiplexer (80).

Abstract: A television system 106 and display method for receiving and displaying television broadcasts having various formats. The television system resizes (106) the various received image formats for display on a common display device. Images are resized horizontally by altering the rate at which data is sampled by the television (106). Images are resized vertically by using vertical scaling algorithms which alter the number of lines in an image. Format detection may be done automatically by decoding information contained in the vertical interval of the television broadcast signal, or by counting the number of lines in each frame. The input format may be indicated by a viewer.

Abstract: A notebook computer (10) includes provides power to a parallel port floppy drive (24) through the parallel port connector (48). The computer (10) includes a power switching circuit (30) which detects whether a printer or floppy drive is connected to the parallel port connector (48). If a floppy drive (24) is connected, the power is enabled through the parallel port connector (48). If a printer is connected, power is disabled through the parallel port connector (48).

Abstract: An electrophotographic subsystem (130) with on-board monitoring and adjusting capabilities. The subsystem contains a photoreceptor, at least one toner dispenser, a light sensor and a processor. The processor monitors either light received from a light-imaging subsystem which is in the system into which the EP subsystem is inserted, the wear on the photoreceptor, or the toner's composition and amount, or all of the above processes. The processor then sends information either via controllers or directly to various subcomponents as operating parameter settings or instructions.