Abstract: The present invention is a method and system which determine signal probability and transfer probability for each node in a netlist describing an electrical circuit; determine, using the signal probability and transfer probability, a fault detection probability for each node; and, using the fault detection probabilities, determine overall fault coverage of the electrical circuit described in the netlist. The method and system of the present invention then, using the fault coverage data, heuristically determine a set of testpoints to be inserted into the netlist which increase the overall fault coverage of the electrical circuit above a predetermined value.

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A line generator (31) for receiving fields of pixel data sampled from a video input signal and for generating additional lines of pixel data so that the display frames will have more lines than the fields. The line generator (31) has a motion detector (31a) that determines, on a pixel by pixel basis, whether some part of the current field is in motion. A motion signal from the motion detector (31a) is used to select between outputs of two or more pixel generators (31b, 31c). One of the pixel generators (31b) provides pixel values that are better suited for display when the image is not in motion. The other pixel generator (31c) provides pixel values that are better suited for display when the image is in motion.

Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).

Abstract: A method of attaching a microchip onto a circuit board is described. The method may include: forming a core portion of thermally conductive and electrically conductive material 50; forming a perimeter portion of thermally conductive and electrically nonconductive material 54; placing the core portion of thermally conductive and electrically conductive material 50 at a site on a circuit board 58 where the microchip 56 will be bonded; placing the perimeter portion of thermally conductive and electrically non-conductive material 54 around the core portion 50 on the circuit board; and attaching microchip component 56 to the core portion 50 and the perimeter portion 54. The method may also include applying a catalyst on the circuit board before attaching the core and perimeter portions. The method may also include curing the core portion and the perimeter portion at 90 degrees C. for 10 minutes and then applying a catalyst on the core portion and the perimeter portion.

Abstract: A hybrid thermal imaging system (20, 120) often includes a focal plane array (30, 130), a thermal isolation structure (50, 150) and an integrated circuit substrate (60, 160). The focal plane array (30, 130) includes thermal sensitive elements (42, 142) formed from a pyroelectric film layer (82), such as barium strontium titanate (BST). One side of the thermal sensitive elements (42, 142) may be coupled to a contact pad (62, 162) disposed on the integrated circuit substrate (60, 160) through a mesa strip conductor (56, 150) of the thermal isolation structure (50, 150). The other side of the thermal sensitive elements (42, 142) may be coupled to an electrode (36, 136). The various components of the focal plane array (30, 130) may be fabricated from multiple heterogeneous layers (74, 34, 36, 82, 84) formed on a carrier substrate (70).

Abstract: It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual part of the system and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

Abstract: A method and structure for improving the thermal conductivity and therefore the heat dissipation of densely interconnected semiconductor circuits, particularly those utilizing low dielectric constant materials by placing a layer of highly thermally conductive material such as diamond film 26 between layers of interconnect metal 22. An embodiment of the present invention allows increased thermal conductivity from the upper levels of metalization to the substrate 10 where structure of the present invention is repeated to form multiple levels of interconnects stacked one upon the other. Further, the diamond layer of the present invention may be used as an effective etch stop or planarization stop. The present invention can be used with known low dielectric constant materials, interlevel dielectrics 30 and planarization techniques with the added benefit of highly thermally conductive diamond film.

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.z Ga.sub.1-z,As (106), next annealing out defects with the Al.sub.z Ga.sub.1-z As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.

Abstract: An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.

Abstract: A method of dynamically interfacing an application processor with a plurality of peripheral ports is shown, including the use of an expanded memory interface for controlling a plurality of memory components for an application processor external to the interface. The application processor is connected to the expanded memory interface, which is in turn coupled to at least one status port to facilitate communication between the application processor and the status port.

Abstract: A method and apparatus are disclosed for self-timing the precharge of bit lines (22) in a memory array. A reference column bit line (26) is charged to create a reference column voltage. The bit lines (22) in the memory array (12) are precharged until the reference voltage exceeds a first threshold.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 and contact vias 23 in a substrate 20; depositing a bias contact metal 32 into the vias 23 forming biasing contact areas around a periphery of the substrate 20; depositing a first trench filler 24 in the trenches 22 and vias 23; replanarizing; depositing a common electrode layer 25 over the thermal isolation trenches and the biasing contact areas; mechanically thinning the substrate 20 to expose the biasing contact area 32 and the trench filler 24; depositing a contact metal 34 on the backside of the substrate 20, the exposed trench filler 24 and the exposed bias contact area; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. The thermal isolation trenches 22 and the bias contact vias 23 may be formed by ion milling or laser vaporization.

Abstract: A method for etching a tapered edge on a cladding layer 10 of an integrated optical waveguide by simultaneously etching a cured droplet of photoresist 16 and the core cladding material to translate the profile of the droplet to the cladding to provide a larger cladding thickness at the interface to the optical fiber 20 and a taper to the cladding thickness needed to control the performance of the integrated optic device. Advantages include selective thinning of the core cladding while maintaining a low loss coupling of the optical fiber to the waveguide core on the integrated device, and higher yield in production during edge polishing.

Abstract: A non-linear torsion hinge (12, 22) for a micro-mechanical device (10, 20) having a hinged movable element (11, 21). Each hinge (22) is comprised of two hinge strips (22a) spaced apart in the same plane, such that the axis of rotation of at least one of the hinge strips (22a) is different from the axis of rotation of the movable element (21). As a result, the hinge strip (22a) must elongate as it twists, thereby providing a greater restoring torque.

Abstract: A network (10) of mobile computing devices (18) communicates by receiving and rebroadcasting messages using wireless transmission. A message is initiated by first mobile computing device and transmitted to a set of other mobile computing devices which may be selected on an ad hoc basis. The receiving mobile computing devices rebroadcast the message to other of the mobile computing devices (18) which have not received the message. The message is repeatedly rebroadcast until all mobile computing devices (18) have received the message or, if the message is intended for particular selected mobile computing devices (18), until all selected devices have received the message.

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The system further includes circuitry (12c) for coupling a clock signal to the clock signal input, circuitry (28) for coupling a first clock adjustment signal to the clock adjustment signal input, and circuitry (24) for comparing the first clock adjustment signal to a second clock adjustment signal. Lastly, the system includes circuitry responsive to the comparing circuitry. This responsive circuitry includes firstly, circuitry (26) for coupling a signal to the clock signal lock input such that the phase locked loop circuit indicates an unlocked state, and secondly circuitry (22, 28) for coupling the second clock adjustment signal to the clock adjustment signal input after the phase locked loop circuit indicates an unlocked state.

Abstract: An electronic device for use in a computer system, and having a small second-level write-back cache, is disclosed. The device may be implemented into a single integrated circuit, as a microprocessor unit, to include a microprocessor core, a memory controller circuit, and first and second level caches. In a system implementation, the device is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access that is a cache hit in the second level cache writes to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed. In addition, each entry of the second level cache is flushed to DRAM upon each of its byte locations being modified.