Abstract: A preferred embodiment of this invention comprises a first thin dielectric buffer layer of a first leakage-current-density material (e.g. strontium titanate 32) with a first moderate-dielectric-constant, a high-dielectric-constant layer of a second leakage-current-density material (e.g. barium strontium titanate 34) overlaying the first thin dielectric buffer layer, and a second thin dielectric buffer layer of a third leakage-current-density material (e.g. strontium titanate 36) with a second moderate-dielectric-constant overlaying the high-dielectric-constant layer, wherein the first and third leakage-current-density materials have substantially lower leakage-current-densities than the second leakage-current-density material. The first and second thin moderate-dielectric-constant buffer layers (e.g. strontium titanate 32, 36) substantially limit the leakage-current-density of the structure, with only modest degradation of the dielectric constant of the structure.

Abstract: This is a method and system of communicating on a data and computer communications network.

Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package(10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Abstract: Methods of reducing artifacts in SLM-based display systems (10, 20), whose images are based on data displayed by bit-weight for pulse-width modulated intensity levels. A first method is suitable for systems (20) that use multiple SLMs (14) to concurrently display images of different colors, which are combined at the image plane. The data for each color are staggered in time (FIG. 4). A second method is suitable for either multiple SLM systems (20) or for systems (10) that use a single SLM (14) and a color wheel (17) to display differently colored images sequentially. The data for each color is arranged in a different data sequence (FIG. 5). In either method, the intensity transitions do not occur at the same time.

Abstract: An electronic system, such as a computer system, having a first level write through cache and a smaller second-level write-back cache, is disclosed. The disclosed computer system includes a single integrated circuit microprocessor unit that includes a microprocessor core, a memory controller circuit, and first and second level caches. The microprocessor unit is connected to external dynamic random access memory (DRAM). The first level cache is a write-through cache, while the second level cache is a write-back cache that is much smaller than the first level cache. In operation, a write access cache miss to the first level cache that is a cache hit in the second level cache effects a write to the second level cache, rather than to DRAM, thus saving a wait state. A dirty bit is set for each modified entry in the second level cache. Upon the second level cache being full of modified data, a cache flush to DRAM is automatically performed.

Abstract: A color wheel (15) for use in a display system (10). The color wheel (15) is comprised of a rigid hub (23) and an outer perimeter of color filter segments (21), which are made from a thin plastic material.

Abstract: An electronic device includes an electronic circuit having points for introducing power supply voltage, ground return, and at least one output. A keyless device package holds the electronic circuit, and the keyless device package is subject to misorientation. Terminals, including terminals for power supply voltage, the ground return and the output, are connected to the electronic circuit and secured to the device package. The terminals are distributed on the device package so that a turning reorientation of the entire electronic device translates the terminals to each other only in a way which prevents electrical stress to the electronic circuit due to possible misorientation of the electronic device under test. Other devices, systems and methods are also disclosed.

Abstract: A membrane device is provided in which a plurality of ridges (14) and recesses (16) are formed proximate to a substrate (12). Electrodes (18) are formed within the recesses (16). A spacer (20) supports a membrane (22). Application of a potential difference between the membrane (22) and the electrodes (18) allows for deflection of the membrane (22) toward the electrodes (18).

Abstract: An architecture for a compact, 1.times.N optical switch. The switch package receives light from an input optical fiber (12b), which is directed over a well or gap at the bottom of which lies a micromechanical structure (10). If the structure is in an unaddressed state, the light travels into an in line output optical fiber (12a). If the structure (10) is in an addressed state, it intercepts the light and reflects it out of the plane of the input optical fiber to an offset mirror (24). The offset mirror (24) then reflects the light to one output fiber (16a, 16b). The offset mirror may have steps such that more than one optical fiber could become the output fiber, depending upon the structure's position.

Abstract: A tracking filter (10,80) which transitions from a type 2 loop to a type 1 loop as the loop error approaches 0 for fast settling and convergence without overshoot or ringing. The filter can either be implemented as an analog circuit (10) in hardware or digitally (80) in software. A first integrator (30) or first accumulator (82) is utilized to increment or decrement a discriminator (22,96) output error value as long as the sign of its output (32) from the previous iteration is the same as a sign of the error signal provided to its input (26) by the error discriminator (22,96). The first integrator output is limited to a range by a limiter (42) between a minimum and maximum value. If the sign of the first integrator output is different from the sign of the input, the contents of the first integrator or accumulator are dumped. The output from the first integrator or first accumulator has binary scaling (44,94) to scale its value before adding it to a second integrator (50) or second accumulator (88).

Abstract: A method and apparatus (10) of aligning color modulation data to color wheel filter segments (13) in a field sequential color spatial light modulator display system. A color wheel (12) having a plurality of colored segments (13) joined at spokes (14) is rotated before a narrow light beam (20). The colored light (22) is observed until light of a mixed color is detected, this light of mixed color corresponding to light of equal portions from the two segments adjacent the spoke. The time between a wheel marker (42) is detected and when the predetermined mixed color is observed is measured. Optical sensors (50) can be utilized to sense a mixed color, such as magenta derived from the combination of a red/blue transition, but also can be done manually by briefly illuminating the wheel to visually ascertain this predetermined color.

Abstract: Higher quality printing is difficult in implementation in spatial light modulator printers. The two major problems are accomplishing gray scale within the line time constraints, and eliminating staircasing artifacts within the images printed (81). It can be improved by using an alternate way of resetting cells on the spatial light modulator when data is being loaded onto the cells, timing delay (86), horizontal offset (84), and differently sized pixels (80, 82).

Abstract: An electronic system (100) includes a register (TONTOFF) for data and a clock circuit (2340, 708) coupled to the register and responsive to the data in the register to generate a series of clock pulses (CPU.sub.-- CLK). The series of clock pulses occupies time intervals (2550) interspersed with time intervals free of clock pulses (2552), as an output having a ratio of the time intervals responsive to the data. Other devices, systems and methods are also disclosed.

Abstract: A DMD spatial light modulator (20) having an improved reset waveform (80) that improves the electrostatic control over the DMD mirrors (30) during switching states (T3). An intermediate bias level is provided to the yoke (32) and mirror (30) during the mirror reset cycle (T3) which is sufficient to maintain a voltage differential between the mirror/yoke and the address electrodes (26,28,50,52) to dynamically park the mirror during a same-state transition, but which voltage differential is insufficient to overcome the hinge restoration forces during an opposite-state transition such that the mirror releases toward the neutral position and can be captured in the other state upon reapplication of the bias voltage. The transition bias level is maintained for a sufficient time period (T3) to allow the mirror/yoke to release from the landing pads (82) a sufficient distance toward the neutral position.

Abstract: There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: A low profile keyboard which can be deployed from a storage position and once deployed have the feel and travel of prior art keyboards using scissor type wobble control. An embodiment of the invention reduces the storage thickness in prior art designs by translating the flexible dome to a position under the keycap when in the stowed position and back to beneath the actuator mechanism when in the deployed position. Thus in the deployed position the space for the key travel and the dome does not contribute to the overall thickness of the keyboard.

Abstract: An improved process for manufacturing semiconductor devices (10). The device, which could be a semiconductor wafer, an individual chip, or a device that has integrated within it semiconductor devices, such as a compact disk drive, is placed or held upside down with its working surface (12) open. The device (10) is struck, causing particulates (18) attached to the working surface (12) to fall free of the device. Alternately, the device could be sharply decelerated to apply the shock. Additionally, the device could be held substantially vertical and rotated to use centrifugal force to separate the particulates away from the device.

Abstract: A method of resetting the mirrors (11, 21) of the mirror elements of a digital micro-mechanical device (DMD) (10, 20). A bias voltage is applied to the mirror elements and the surface upon which they land, but is removed after the address voltage has been switched. (FIG. 4). Immediately before the bias is removed, a reset voltage is added to the bias voltage. The reset voltage signal is comprised of a number of pulses at a frequency that matches the resonant frequency of the mirrors. The magnitude of the reset voltage results in a total applied voltage that permits vibrational energy to build but that is insufficient to cause the mirrors to become unstuck until the end of the reset signal. In other words, the magnitude of the reset voltage is small relative to that of the bias voltage.

Abstract: An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ N-type MOSFETS, CMOS transfer gates or tri-state inverters in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.

Abstract: A process flow which can be used to fabricate a high frequency bipolar transistor 147, a power transistor 146, and non-power MOS devices on a single substrate while maintaining superior performance. The process flow forms an initial high-voltage tank 170 in substrate 150. A thin epitaxial layer 156 is formed on the substrate which overlies the initial high voltage tank and Diffusion Under Film, DUF, region 154. The high voltage tank is extended through the epitaxial layer and power transistor 146 is formed in the high voltage tank and high frequency bipolar transistor 147 is formed in the epitaxial layer using the DUF region as a deep collector. Other types of low voltage devices 139 and 140 and mid voltage devices 141-145 and 148-149 are formed unaffected by the presence of epitaxial layer 156. A single chip transmitter 400 and a single chip receiver 410 is fabricated with high frequency transistors and power devices.