Patents Represented by Attorney, Agent or Law Firm James H. Fox
  • Patent number: 6275090
    Abstract: An integrated circuit includes a self-calibrating resistor circuit comprising a resistor string, a comparator, a state machine, a reference voltage source, and a reference current source. The current source typically comprises a voltage reference, typically a bandgap reference, and a temperature-independent resistor having a value REXT. In operation, a reference current IREF flows through the resistor string. During a calibration period, the voltage across the string is compared to the bandgap reference voltage, VBG, by the comparator, which controls the state of the state machine. The outputs of the state machine turn on or off the resistors in the string until the voltage across the string, VR, is approximately equal to the reference voltage. The resistance of the resistor string is then equal to RBG=VBG/IREF, which is proportional to REXT, and thus is typically independent of process and temperature.
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: August 14, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Harley Franklin Burger, Jr., Jeffrey Lee Sonntag, Suharli Tedja
  • Patent number: 6147520
    Abstract: An integrated circuit includes a controlled impedance that remains relatively constant with respect to variations in processing and temperature. The controlled impedance comprises a fixed resistor in parallel with one or more switchable resistors having a resistance value greater than that of the fixed resistance. Control circuitry includes a reference current generator. The reference current is flowed through a tracking resistor formed of the same material (e.g., doped polysilicon) in the same fabrication process as the fixed resistor. Comparators are used to monitor the voltage across the tracking resistor, and control the switching of the switchable resistors in order to obtain a desired effective resistance. Use of the inventive technique to provide a transmission line termination impedance is described in an illustrative embodiment.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: November 14, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Makeshwar Kothandaraman, Wayne E. Werner
  • Patent number: 6141252
    Abstract: An integrated circuit has an improved voltage regulator for use with memory devices that utilize secondary electron injection for programming. The memory device, typically a floating-gate EEPROM, has source and drain regions formed in a doped tub region. A first voltage source is used to reverse-bias a diode, formed in the same process as the source and drain regions of the memory device, to near the breakdown voltage. A small bias current flows through the reverse-biased diode from the first voltage source to a second voltage source, thereby establishing a reference voltage. The drain voltage of the memory device is then biased, typically by a bipolar transistor, to about a diode drop (about 0.7V) below the reference voltage, and hence correspondingly below the drain-to-tub breakdown voltage of the memory device. In this manner, the reference voltage tracks changes in the memory device due to process variations, temperature variations, etc.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: October 31, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Chun Chen
  • Patent number: 6091657
    Abstract: When flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires higher voltages to be applied to the flash memory device. In a typical design, during tub erase 10 to 12 volts is applied to the tub, source and drain, and -6V is applied to the control gate of the flash memory device. However, in the state-of-the-art CMOS processes (usually used at a power supply voltage 3.3 V and below), it is difficult to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. Therefore, the required HV devices prevent tub erase from being widely used, especially for embedded applications.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: July 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Chun Chen, Richard Joseph McPartland
  • Patent number: 5969421
    Abstract: An integrated circuit and method of use provides conductive vias between conductor layers so that current flows in such a manner that current crowding is reduced in at least one underlying layer. In particular, the current flows from an overlying conductor (306) down to an underlying conductor (303) by a first set of vias (307), and a portion flows through the underlying conductor towards the destination (e.g., a bondpad). Another portion of the current flows downward to a still lower conductor by means of a second set of vias (310, 311). The second set of vias is located further away from the destination than the first set of vias. Current crowding in the underlying conductor is thereby reduced. An integrated circuit utilizing the inventive technique typically has transistors formed in the semiconductor substrate, wherein at least one of the electrodes (e.g.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: October 19, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Yehuda Smooha
  • Patent number: 5926056
    Abstract: An integrated circuit output buffer has an improved tolerance to voltage levels that are greater than the power supply voltage level at which the IC is designed to operate. A first transmission gate transistor (110), typically p-channel, is connected between an output conductor (101) and a resistor (108) at a given node (114). The node is also connected to the gate of a second transmission gate transistor (105), typically also p-channel. The resistor pulls the given node towards a power supply voltage level (e.g., ground), so that the second transmission gate transistor conducts in normal operation. To prevent the node from reaching ground, at least one diode-like voltage-dropping device (201, 202) is connected in series with the resistor.
    Type: Grant
    Filed: January 12, 1998
    Date of Patent: July 20, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Bernard Lee Morris, Bijit Thakorbhai Patel
  • Patent number: 5909557
    Abstract: A technique for configuring a processor allows the processor to interface with external buses of different types; for example, busses having different data widths. Configuration data is stored in a memory, typically a read-only memory, and transferred to the processor during a system configuration period. An initial configuration fetch may be accomplished to retrieve the configuration information prior to executing an actual processor instruction. Alternatively, the configuration information may be included in an actual instruction word. The system configuration period typically occurs during the initial power-on sequence, but may occur at other times.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: June 1, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Michael Richard Betker, Trevor Edward Little
  • Patent number: 5889419
    Abstract: A differential comparison circuit obtains an improved common mode range with respect to the voltages on first and second inputs. A first comparator is activated when the first and second input voltages are above a first level. A second comparator is activated when the first and second input voltages are below a second level. The output of the comparator that is activated is selected for providing the comparison output signal. In this manner, the comparator having improved performance, typically in terms of differential input voltage sensitivity, may be selected for the voltages present at the inputs. In a typical embodiment, the first comparator uses n-channel input devices, and the second comparator uses p-channel input devices. The activation is provided by voltage level-sensing circuitry, and may include hysteresis to help ensure reliable operation.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: March 30, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Jonathan Herman Fischer, Bernard Lee Morris
  • Patent number: 5859564
    Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: at least one differential amplifier. The differential amplifier is coupled in a circuit configuration so that the differential output voltage signal of the differential amplifier circuit includes a scalable second-order harmonic component of the differential input voltage signal applied to the differential amplifier circuit. Briefly, in accordance with another embodiment of the invention, a method of applying a differential input voltage signal to a differential amplifier circuit to produce a differential output voltage signal includes the step of: driving the differential amplifier circuit so that the differential output voltage signal of the differential amplifier circuit includes a second-order harmonic component of the differential input voltage signal.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: January 12, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Jeffrey Lee Sonntag, Suharli Tedja
  • Patent number: 5838033
    Abstract: A doped semiconductor distributed resistor is placed in series with the drain of a field effect transistor, typically for electrostatic discharge protection of an integrated circuit. The resistor is defined with a mask formed from the same conductor layer (e.g., polysilicon) that forms the transistor gate conductor. To avoid a floating gate, the conductor mask may be tied to the associated output bondpad. The advantages of using a gate conductor-defined resistor as compared to the prior-art practice includes better control of the resistor dimensions. Hence, the overall size of the output transistor and resistor may be reduced as compared to prior-art techniques, while achieving a high level of ESD protection.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: November 17, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Yehuda Smooha
  • Patent number: 5828251
    Abstract: An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: October 27, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Ronald Lamar Freyman, Michael James Hunter
  • Patent number: 5818262
    Abstract: A integrated circuit buffer includes a first inverter comprising a pull-up transistor of a first conductivity type (e.g., p-channel) and a pull-down transistor of a second conductivity type (e.g., n-channel) for driving a load. The buffer further includes a second inverter comprising a pull-up transistor of the second conductivity type (e.g., n-channel) and a pull-down transistor of the first conductivity type (e.g., p-channel) that also drives the load. The first and second inverters are driven by a drive circuit that provides signals that are substantially out of phase. Therefore, in operation the pull-up transistors are active during a first time period, and the pull-down transistors are active during a second time period. In this manner, the drive capability of the buffer is improved in the face of voltage bounce on the power supply bondpads, which is typically due to package inductance.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: October 6, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Juergen Pianka
  • Patent number: 5808480
    Abstract: An integrated circuit output buffer that is fabricated using a relatively low voltage technology is capable of driving a relatively high voltage swing to an output conductor. For example, a buffer implemented in 3.3 volt CMOS technology can deliver a 5 volt output swing. This is achieved by scaling up the output voltage swings from the lower voltage level to the higher voltage level using one or more intermediate inverters that operate at successively higher voltage levels. In a preferred embodiment, the voltage levels are provided using a power conservation circuit that limits current flow through a resistor voltage divider network.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: September 15, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Bernard Lee Morris
  • Patent number: 5744993
    Abstract: Briefly, in accordance with one embodiment of the invention, a device for use in a magnetic recording read channel adapted to be coupled to a magneto-resistive (MR) read head comprises: an integrated circuit adapted so as to introduce a controllable amount of second-order nonlinearity into the magnetic recording read channel signal path to at least partially offset nonlinearity associated with use of the MR read head. Briefly, in accordance with another embodiment of the invention, a method of reducing nonlinear signal effects in a magnetic recording read channel signal path associated with use of a magneto-resistive (MR) read head comprises the step of: introducing into the read channel signal path a scalable square of the read channel signal.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: April 28, 1998
    Assignee: Lucent Technologies, Inc.
    Inventor: Jeffrey Lee Sonntag
  • Patent number: 5719449
    Abstract: An integrated circuit is adapted for implementing flip-chip technology with solder bumps, while providing for improved testability. The integrated circuit comprises two sets of pads formed in the same metal layer, with a first set being used for wafer probing, and a second set for solder bumps. The wafer probe pads are placed in one row along each chip edge. A second set of pads, the solder bump pads, are arranged in rows towards the center of the chip with respect to the wafer probe pads. Metal interconnects formed in the same metal layer as the pads connects each solder bump pad to a corresponding wafer probe pad. Testing of the integrated circuit may be accomplished using the wafer probe pads according to conventional techniques, while mounting of the chip may be accomplished with the solder bump pads using the flip-chip technology.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: February 17, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Mark Steven Strauss
  • Patent number: 5694444
    Abstract: An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: December 2, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Sonali Bagchi, Jalil Fadavi-Ardekani, Kenneth Daniel Fitch, Daisuke Takise
  • Patent number: 5663677
    Abstract: An improved integrated circuit conductor layout technique provides lower and upper conductor levels that bound circuit blocks and provide for power supply voltage distribution to the circuitry in the circuit blocks. The lower and upper conductor levels also provide for first and second groups of parallel signal conductors in wiring channels between circuit blocks. An intermediate conductor level is located between the lower and upper conductor levels, and conducts power supply voltages between adjacent circuit blocks. The power supply conductors formed in the intermediate conductor level also serve to isolate the signal conductors in the lower conductor level from the signal conductors in the upper conductor level (and vice-versa) in the wiring channel. This isolation typically improves the design of the integrated circuit by providing more reliable estimates of signal propagation in the wiring channels.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: September 2, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Ronald Lamar Freyman, Ted R. Martin, Steven Paul Pekarich
  • Patent number: 5651055
    Abstract: A telephone answering machine and method of use utilizes speech recognition to identify a caller from a pre-defined list of possible callers. The list may be generated by various input techniques, including a spoken voice at the called party's location, and keyboard or graphical input techniques. If the caller is identified as being on the list, the machine allows the call to progress along a first sequence, which includes ringing the called phone. If the called phone does not answer, the first sequence may provide for responding with a customized message for the calling party. If the caller is not identified as being on the list, the machine allows the call to progress along a second sequence, which includes responding with a standard recorded message. In either case, the caller is typically allowed to record a message for the called party. Additional pre-defined lists may be provided, as for determining the context of a call.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: July 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Pramod Vasant Argade
  • Patent number: 5623217
    Abstract: A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Barry K. Britton, Kai-Kit Ngai, Satwant Singh
  • Patent number: RE37569
    Abstract: A modem that operates reliably at a symbol rate that corresponds to twice its bandwidth even when it is coupled to a receiving A/D converter that operates under control of a clock is realized by synchronizing the modem's operation to the A/D's clock. The superior operation of this modem advantageously extends to A/D clock frequencies beyond the frequency of twice the modem's bandwidth. To minimize quantization noise, the modem's output is conditioned to minimize intersymbol interference by adjusting the modem's output to the A/D converter's sampling times and slicing levels. When the A/D's clock is higher than twice the bandwidth of the modem's output signal, some intersymbol interference cannot be avoided. In accordance with this invention, the position and value of this interference is computed at the receiver and subtracted from the received signal.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: March 5, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Ender Ayanoglu, Nuri Ruhi Dagdeviren, James Emery Mazo, Burton Reuben Saltzberg, Irving Kalet