Patents Represented by Attorney, Agent or Law Firm James H. Fox
  • Patent number: 5412606
    Abstract: An integrated circuit memory array includes column conductors that are precharged during a precharge period in order to reduce the effects of power supply voltage variations, a load resistor is connected between the column conductors and ground during a portion of the precharge period. In this manner, a voltage-divider is formed that provides a discharge path which prevents over-charging of the column conductors. An increase in power supply noise immunity is gained, thereby avoiding degradation of the worst-case memory access time that could otherwise occurs.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: May 2, 1995
    Assignee: AT&T Corp.
    Inventor: Kang W. Lee
  • Patent number: 5406592
    Abstract: A circuit includes both a frequency locked loop (FLL) and a phase locked loop (PLL) to control the frequency and phase of a controlled oscillator with respect to a data signal. The FLL includes a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of the controlled oscillator to equal the frequency of the data signal. The PLL has a phase detector for causing the phase of the controlled oscillator to approximate the phase of the data signal. The inventive circuit also includes a lock detector for determining whether the phase error between the controlled oscillator and the data signal is constant. When phase lock is achieved, a counter is enabled to count a periodic reference signal and to produce an overflow signal when a given count is exceeded. The overflow signal is selectively coupled to the frequency setting register in order to reduce the phase difference between the controlled oscillator and the data signal.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: April 11, 1995
    Assignee: AT&T Corp.
    Inventor: Robert J. Baumert
  • Patent number: 5406247
    Abstract: The median value of a set of voltage values is found by a technique that minimizes the circuitry while maximizing the speed, and also provides for dropouts. The voltage values, illustratively five in number, are applied in pairs to the inputs of ten comparators. The outputs of the comparators, and their complements, are formed into five "status words" of four bits each, such that each bit of a given status word represents the comparison of a given value with another of the values. The status word that contains two 1's and two 0's represents the median value. In a preferred circuit embodiment, this status word is rapidly determined in a series of three logic stages, wherein the highest and lowest values are eliminated in the first stage, the next highest and lowest are eliminated in the second stage, and the last stage determines the remaining status word that is associated with the median value. This technique also readily provides for dropouts by initializing the logic circuitry.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: April 11, 1995
    Assignee: AT&T Corp.
    Inventor: Krishnaswamy Nagaraj
  • Patent number: 5396126
    Abstract: A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as "Switching R-nodes". The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: March 7, 1995
    Assignee: AT&T Corp.
    Inventors: Barry K. Britton, Dwight D. Hill, William A. Oswald
  • Patent number: 5384497
    Abstract: Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: January 24, 1995
    Assignee: AT&T Corp.
    Inventors: Barry K. Britton, Dwight D. Hill, William A. Oswald
  • Patent number: 5356659
    Abstract: A low temperature chemical vapor deposition process is used to encapsulate aluminum conductors on the surface of a silicon substrate to form bimetallic conductors. The refractory material is desirably tungsten.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: October 18, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Desu Seshubabu, Hans P. W. Hey, Ashok K. Sinha
  • Patent number: 5355369
    Abstract: The use of the JTAG port provides for boundary scan testing of integrated circuits, thereby allowing for the testing of IC's after they have been mounted into a circuit board. However, the conventional JTAG scheme is limited as to speed, since both the input and output vectors must be serially shifted in and out of I/O buffers along the chip boundaries. The present invention speeds the testing of high-speed core logic circuitry by transferring the test program to a special test data register, which downloads the program to the logic circuitry under test, and uploads the results. This allows the core logic to perform the test at its normal operating speed, while still retaining compatibility with the JTAG standard for other tests.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: October 11, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Alan J. Greenberger, Homayoon Sam
  • Patent number: 5345419
    Abstract: A first in, first out memory (FIFO) includes a multi-port memory array, which is accessed for read/write operations by activating a selected read or write word line. The read word line is controlled by a read shift register, and the write word line is controlled by a write shift register. In order to generate "full" and "empty" flags, the voltage state of read and write word lines are determined in "match circuits", which compare the locations of the read and write pointers. This eliminates the use of counters, and allows the shift registers and word line match circuits to be an integral part of a single-block regular structure. Furthermore, it allows the FIFO to be readily expanded to multiple numbers of words and bits per word.
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: September 6, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Larry R. Fenstermaker, Kevin J. O'Connor
  • Patent number: 5345356
    Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). To assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel pre-driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: September 6, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Juergen Pianka
  • Patent number: 5345357
    Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, a capacitor couples a bond pad to the gate of a protective transistor that applies a turn-on voltage to the gate of an n-channel output transistor. In this manner, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). In one embodiment, to assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: September 6, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Juergen Pianka
  • Patent number: 5334885
    Abstract: The number of active switching elements in a buffer is automatically varied to compensate for variations in the manufacturing process, operating temperature, and power supply voltage. For this purpose, a reference voltage which is proportional to the speed of a switching transistor is applied to an analog-to-digital (A/D) converter. The A/D converter may be implemented with a simple resistor divider and comparators, all of which can be made on-chip. The resistor dividers are chosen such that at worst-case slow conditions all the comparators have high outputs. As the process/temperature/voltage changes, the reference voltage also increases. This successively turns off sections of the switching transistor, thereby slowing down the response of the buffer. Since the control leads are digital, they are not susceptible to noise as they are routed around a chip full of noisy signals. The digital control signals may be latched, and the control circuitry powered down to zero for powersensitive applications.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: August 2, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Bernard L. Morris
  • Patent number: 5311084
    Abstract: Process, voltage, and temperature variations affect the noise generation of an output buffer. Controlling the switching speed of the buffer over these variations also controls the buffer noise, which may be due to ground bounce or other reasons. In one prior-art technique, the current flow behavior of a static circuit is used to control the rise and/or fall times of the output buffer. However, accounting for all possible variations in the factors that influence the switching speed is difficult with a static control circuit. In the inventive technique, the AC switching behavior of a scaled-down buffer that is driven by a periodic signal generates the control voltage. In this manner, the factors that influence buffer switching speed, including process, voltage, and temperature variations, may be more accurately accounted for.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: May 10, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Thaddeus J. Gabara
  • Patent number: 5311088
    Abstract: Analog filters may be conveniently implemented in MOS technology by the use of "transconductance cells". Each cell includes stages each having a pair of current paths, with each path comprising a current source and input transistor. The gain of each stage is set by a transistor connected across the current path, with the transconductance of this transistor being controlled by its gate voltage. In the inventive technique, a transconductance cell comprising two input stages utilizes inputs to each input stage that are in-phase rather than complementary, as in prior-art designs. The inputs to the second input stage are then each balanced (out of phase) with respect to the inputs to the first input stage. Higher linearity is obtained, with the common-mode signal being cancelled by the summation of currents supplied by the input stages to the common output stage. A biquadratic filter conveniently implements this technique, with other applications being possible.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: May 10, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Dale H. Nelson
  • Patent number: 5311080
    Abstract: A field programmable gate array that includes a dedicated path that directly connects an I/O pad to a selected register in the array of programmable function units. For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver, to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: May 10, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Barry K. Britton, Dwight D. Hill, William A. Oswald
  • Patent number: 5304839
    Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: April 19, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Che-Tsung Chen, Thaddeus J. Gabara, Bernard L. Morris, Yehuda Smooha
  • Patent number: 5305443
    Abstract: A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and there are no pending bus transactions. When this state is entered, the data just read from the data bus is driven back onto the data bus, and the device which had provided the data is placed in the tri-state (high-impedance) condition. This loop-back feature, combined with the fact that all other outputs are held at their previous values, provides for near-zero power dissipation on the bus. The inventive technique avoids the use of pull-up resistors, which are provided on prior art tri-state busses to ensure that the busses do not float and enter the threshold region where high power dissipation occurs.
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: April 19, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Robert T. Franzo
  • Patent number: 5304867
    Abstract: Prior-art high speed TTL-to-CMOS input buffers consume a large amount of power supply current through the input transistors when the input voltage is held at a mid-range level between V.sub.DD and V.sub.SS (e.g., 2.0 volts). The inventive input buffer includes a resistance in series with the p-channel pull-up transistor on the input inverter, in order to limit this current. In addition, to retain high operating speed, a p-channel shunt transistor is placed in parallel with the resistance, and controlled by the buffer output signal. This shunt transistor effectively bypasses the resistance from the circuit when the buffer output goes low, thereby providing high operating speed.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: April 19, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Bernard L. Morris
  • Patent number: 5298436
    Abstract: A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.
    Type: Grant
    Filed: June 16, 1993
    Date of Patent: March 29, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Joseph R. Radosevich, Pradip K. Roy
  • Patent number: 5289025
    Abstract: A wide variety of integrated circuit applications exist for boosted nodes, wherein a voltage is boosted above the power supply level. Typical uses include clock driver circuits in microprocessors, row lines in dynamic and static memory chips, and substrate bias generators. However, in the prior art, only n-channel transistors have been usable to boost nodes above the positive power supply level, to prevent forward-biasing the drain-to-substrate diode. The present invention allows a p-channel device source/drain region to be connected to a boosted node. This is accomplished by also boosting the voltage of the n-tub in which the device is formed, thereby allowing the p+ source/drain regions to be boosted without latch-up or other problems. Similarly, n-channel devices may be connected to nodes boosted more negative than V.sub.SS.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: February 22, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Hyun Lee
  • Patent number: 5282174
    Abstract: A dual-port memory is accessed via a fast read port through p-channel access transistors and via a slow read/write port through n-channel access transistors. To reduce the disturbances resulting from a read operation through the read/write port, the row-line voltage applied to the gates of the n-channel access transistors is reduced to a value (e.g., 3 volts) below the value used for a write operation (e.g., 5 volts). In this manner, the lowered conductance of the n-channel access transistors during a read operation minimizes the effects of the pre-charged column conductors on the memory cell. Problems that could occur with a simultaneous read from the fast port, among others, are reduced.
    Type: Grant
    Filed: January 31, 1992
    Date of Patent: January 25, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Trevor E. Little