Abstract: A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.

Abstract: An integrated circuit includes a gain control terminal that provides for a choice of discrete gain values for circuitry on the IC. Typically, the gain control terminal is connected to a high voltage source (V.sub.DD), or a low voltage source (V.sub.SS), or optionally left unconnected. In addition, the integrated circuit provides a gain set terminal for connection to an external impedance, typically a resistor, and also includes gain set circuitry for determining the value of the resistor as falling within one range out of several possible ranges. Based upon the range thus determined, the gain set circuitry selects the discrete gain values that are available for choice by the gain control terminal. In this manner, a large range of gain values are available for use even though only a few need to be selected in actual operation of the IC. This technique minimizes external package terminals for the IC, and allows for gain setting by low tolerance resistors.

Abstract: A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of reducing the power consumption of a pipelined signal processor embedded in an integrated circuit (IC), after applying power to the IC, comprises the step of: applying a sufficient number of internally generated clock pulses to the pipelined signal processor so as to place at least one bus in the signal processor pipeline in a predetermined state. Briefly, in accordance with another embodiment of the invention, an integrated circuit comprises: a power-up reset circuit for a pipelined signal processor. The power-up reset circuit includes a counter and a digital signal oscillator. The digital signal oscillator and counter are coupled in a configuration so as to provide a predetermined number of clock pulses substantially in response to a power-up signal. The configuration is adapted to be coupled to the pipelined signal processor.

Abstract: An integrated circuit ESD protection technique includes a protection circuit having a series resistor-capacitor circuit connected between power supply bondpads. The resistor-capacitor circuit provides a desired time constant for control of active drive circuitry that controls a protective transistor also connected between the bondpads. The time constant is chosen to be short enough to prevent conduction of the protective transistor during normal operation and power-up, while still allowing conduction of the protective transistor during the initial phase of an ESD event. A feedback resistor is connected in parallel with the active circuitry, thereby lengthening the time that the protective transistor conducts during an ESD event. In this manner, the ESD current is more completely conducted through the protective circuitry, so that the level of protection is increased.

Abstract: A field programmable gate array (FPGA) with a programmable function unit (PFU) that includes a look-up table (LUT) for implementing a plurality of functions including first and second RAM cells, and a programmable switching device dedicated to coupling and decoupling the RAM cells. The first and second RAM cells are coupled to respective first and second read/write ports. The RAM cells function individually as single-port RAM cells when decoupled by the switching device. However, the RAM cells share data to function collectively as a dual-port RAM cell when coupled by the switching device. The dual-port RAM cell is accessible by both the first and second read/write ports.

Abstract: A fast, low power and small size approach to matching digital patterns provides for comparing of the input pattern bit-by-bit against the reference pattern to determine matches. In the illustrative embodiment, each mismatch turns on a current source. When the current from mismatches exceeds a maximum current sink value, the pattern mismatch output goes high. Both the reference pattern as well as the number of bits that must match may conveniently be made programmable. This approach is especially useful in "fuzzy" matching, where any N bits of an M bit pattern must match to consider the pattern matched.

Abstract: Silicon wafers oriented in the (100) crystal planes are sawed from a silicon ingot using the (111) faces on the as drawn silicon ingot as reference planes. The reference planes permit determination of the ingot orientation during the sawing process.

Abstract: Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor.

Abstract: A novel mad/write control register uses the same bus port for reading and writing, while requiting only one unique control line. The technique may be implemented as a "D" type level sense latch. The write operation is similar to standard latch operation: the transmission gate on the D input is turned on while the feedback transmission gate is off. However, for read operation, both transmission gates are enabled, thereby allowing the register output value to drive the bus. A preset or clear capability may optionally be provided. This approach reduces the size of the register as compared to standard read/write registers, and requires only one unique control line versus two, thus reducing decoding logic and routing. Since only one port to the bus is required, the bus load gate capacitance is typically one-half that of the standard approach.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: CODECs and various other types of communication devices require timing information to enable them to transmit and receive digital information at the proper time. In the case of multiple CODECs on a single integrated circuit, this has typically required devoting terminals to provide separate transmit and receive frame synchronization pulses for each CODEC. Alternatively, a microprocessor interface may be included so that internal registers can be loaded with transmit and receive timing information. However, that approach limits timing flexibility. In the present invention, a "frame synchronization separation pulse" (FSEP) provides the separation in time between transmit and receive synchronization pulses. In this manner, the number of integrated circuit terminals required for synchronization may be reduced.

Abstract: An integrated circuit obtains improved ESD protection by way of a shunt protection circuit having a trigger level that exhibits a hysteresis effect with respect to voltage applied to the bondpads. The hysteresis is obtained by a string of voltage dropping transistors that produce a trigger voltage level at an intermediate node, and a shorting transistor that effectively removes at least one transistor from the string. In a typical case, a PNP bipolar transistor serves as the protective device in the circuit to carry the ESD current from the bondpads. An illustrative embodiment with p-channel voltage dropping transistors and an n-channel shorting transistor is shown, along with additional capacitive boost circuitry for speeding up circuit operation. In this manner, a high peak ESD current can be carried while ensuring non-conduction of the protection circuit for normal operating voltages, and also for voltages slightly in excess of normal power supply voltages.

Abstract: A clocked comparator circuit compares the primary and backup power supply voltages to a system. When the primary voltage falls a given amount below the backup, the circuit provides a signal that may be used to switch to the backup power supply. When the primary voltage is again present, the circuit can switch back to primary power. Alternatively, or additionally, a signal may be generated to initiate graceful shutdown of the system. The clock to the comparator typically operates at a higher frequency when operating on the primary voltage, and a lower frequency when operating on the backup voltage. This circuit is typically used with a portable system that uses a rechargeable battery as its primary power supply. The backup power supply may be a long-life battery that provides power to only a portion of the system. For example, in a computer, only a static memory may be powered by the backup, to allow the full system to retain its proper configuration when the primary power supply is again activated.

Abstract: An integrated circuit includes a digital signal processor (DSP) and an error correction co-processor (ECCP) that implements a Viterbi decoding function. The DSP and ECCP share a block of multi-port memory, typically by bus multiplexing a dual-port RAM. When the ECCP possesses the RAM, it inhibits the DSP from accessing that block of the RAM by asserting an EBUSY flag. This technique conserves and optimizes the RAM usage, allowing the DSP and ECCP to advantageously be formed on the same integrated circuit chip.

Abstract: Perimeter material is removed from substrates by stacking the substrates and subjecting them to a plasma etch. In an exemplary application, the perimeter of a silicon wafer dielectric cap (typically silicon nitride) is removed by stacking the wafers in intimate contact, and etching the wafers in a barrel etcher. A well-controlled removal of the cap perimeter is obtained, allowing for a smooth epitaxial deposition at the water edge in a subsequent operation. An additional benefit is smoothing of the substrate edge contour, which reduces scratching of wafer cassettes and other handling equipment.

Abstract: An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.

Abstract: An application specific integrated circuit (ASIC) clock driver is built under the power supply second level (metal2) buses, with the p-channel and n-channel transistors lying under the V.sub.DD and V.sub.SS buses, respectively. The transistor gates in the clock driver are placed orthogonally with respect to the transistor gates in the polycells. This allows for easy access to the metal2 bus and eliminates the need for the clock driver transistors to "add to" the current flowing through the first level (metal1) V.sub.DD /V.sub.SS buses in the polycell row. Therefore, electromigration concerns are reduced for: (1) the core logic polycells; (2) within the clock driver itself; and (3) on the metallization of the output of the clock driver, since the clock driver typically drives large capacitive loads. The orthogonal layout scheme also allows for full contact of the transistors source and drain regions to the corresponding metal bus, providing for low series resistance.

Abstract: Frequency generators that may be programmed are utilized in a wide variety of applications. Typical applications include radio and television receivers and transmitters, and computer devices that must operate at different clock rates, or be compatible with systems that operate at different clock rates. The present technique provides for programmably generating a frequency. A ring oscillator receives at least one operating voltage through a programmable array of field effect transistors. Digitally selecting a given set of the transistors provides a given operating current for the ring, which establishes the frequency of operation. In one embodiment, the technique is implemented in a CMOS integrated circuit. This technique provides for more rapid frequency changes in a low-power circuit than can be obtained with typical prior-art techniques (e.g., a phase-locked loop).

Abstract: A signal processing system includes means for performing a logic function on a multi-dimensional array of information stored in a memory. Typically, the memory stores two-dimensional video information (pixels), and the logic function is a discrete cosine transform (DCT), or other linear operation. The logic function is performed on both rows and columns of the information. In the prior art, this has required two memory spaces, so that information could be written into one memory while being read out of another memory. In the present invention, a single memory space is used to transpose the information between row and column format, by performing a read-modify-write operation on each memory location in a specified sequence.