Abstract: A silicon-on-insulator MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to the gate electrode. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional mask steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions can be used for the formation of the contact region.

Abstract: A method is provided for forming a contact plug (40) in a contact (34) on a semiconductor substrate (30). A dielectric layer (32) is applied to the substrate (30) and then etched to form the contact (34). A layer (38) is then formed over the dielectric (32) and the contact (34). The layer (38) is removed from all surfaces, except the vertical sidewalls (36) within the contact (34). A metal plug (40) is then deposited in the contact (34) forming cup-shaped layers (42). The nonselectivity of the layer (38) allows the metal of plug (40) to be applied to the contact (34) without encroaching upon the substrate (30) or forming bumps on the surface (44) of the dielectric (32).

Abstract: A metal stud (24) is provided for interconnecting levels of metallization separated by an insulator on a semiconductor slice (10). A lead (12) is coated with a refractory metal (14) and a platable metal cap (16). A photoresist (18) is then applied and a cavity (22) is formed within the photoresist (18). The cavity (22) is plated to form the stud (24). The stud (24) is clad with a corrosion resistant layer (28).

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter structure (60). A collector region (90) and an extrinsic base region (100) are formed in the semiconductor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: The disclosure relates to a MOSFET-protected nonvolatile capacitor cell which has a storage gate and a nonvolatile stack thereunder, the cell having a heavily doped n+ ring surrounding the storage gate and an n-type tank disposed beneath the stack and electrically connected to the n+ type ring.

Abstract: A resistor (10) includes a resistive filling (28) formed within a trench (12) and separated therefrom by an insulating layer (26). Resistive filling (28) is of the same type of semiconductor material as that of second layer (22), but of an opposite extreme of dopant concentration. A head region (32) may be formed below interface (30) within second layer (22) to more clearly delineate the edge of resistive filling (28) from second layer (22). Where resistive filling (28) is of a low dopant concentration, low resistance contact region (34) is formed of a high dopant concentration in order to provide a minimum resistance contact to resistive filling (28).

Abstract: A computer system uses security labels for evey word in memory. Each access to a memory location requires that the security level of the memory location be compared to that of a process which is making the access. If the security level of the process does not dominate that of the memory location, access is denied. Each time a memory location is modified, it is assigned a security level consistent with the levels of all of the data which was used to modify the memory location.

Abstract: Films of Hg.sub.1-x Cd.sub.x Te grown at low temperatures by MBE or MOCVD are homogenized by annealing at about 350.degree. C. for 1.25 to 3 hours.

Abstract: An output circuit is provided which contains voltage control circuitry (14) which drives the gates of the output transistors (18,20) such that the change in current remains relatively constant. The desired voltage output of the voltage control circuitry (14) can be implemented for a CMOS device using N channel and P channel transistors having their gates connected to V.sub.cc and ground respectively. The amount of current control may be adjusted to compensate for environmental conditions such as temperature or voltage supply either dynamically or prior to use.

Abstract: A tunneling device (50) with the emitter (62) to collector (58) current transported by resonant tunneling through a quantum well (52) and controlled by carriers injected into the well (52) from a base (60) is disclosed. The injected carriers occupy a first energy level in the well (52) and the resonant tunneling is thorough a second energy level in the well (52) thereby separating the controlled carriers from the controlling carriers. Three-terminal tunneling devices using three different bandgap semiconductor materials to segregate controlling carriers from controlled carriers are disclosed.

Abstract: A process for fabricating an integrated circuit with both bipolar and CMOS transistors is disclosed. Buried n-type and p-type layers are diffused into a substrate, and a substantially intrinsic epitaxial layer is formed above the buried layers. N-wells and p-wells are formed into the epitaxial layer self-aligned relative to one another, over their respective buried layers. The intrinsic epitaxial layer allows the formation of the p-well, into which n-channel MOS transistors are eventually formed, with minimal mobility degradation due to counterdoping. Isolation oxide regions are formed at the boundaries of the wells, for isolation of the wells relative to one another. Trench isolation may alternatively be used, such trenches including polysilicon plugs which are recessed into the trench, and filled with an oxide layer to allow the placement of contacts over the trench with minimal overetch-induced or stress-induced leakage.

Abstract: An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

Abstract: A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.

Abstract: The disclosures relates to a method of forming an array of small apertures in an aluminum foil for receiving semiconductor spheres in said aperature. The apertures are formed by embossing the foil at the locations of the apertures to provide worked metal regions of reduced thickness at said locations. The foil is then etched in toto, etching taking place more rapidly at the worked metal region. Also, due to the reduced thickness of the foil at the embossed regions, such regions are etched away to provide apertures before the remainder of the foil undergoes material metal loss to provide the desired aperture array.

Abstract: A system (10) is disclosed which tunes a result (14) of a process (12) relative to a reference (16). The system (10) uses two control parameters (C.sub.1 and C.sub.2) which are controlled by a switch (20). The control parameters (C.sub.1 and C.sub.2) are controlled such that only one of the two is acting upon the process (12) to alter the result (14) at any one time.

Abstract: A temperature compensation circuit (FIG. 5a) has a controlled temperature compensated voltage drop across R1. A Schottky diode D1 is connected to the base of Q1 through resistor R1. The temperature coefficients of the base-emitter junction of Q1 and the diode D1 have a predetermined differential, preferably none. The forward voltage drop across D1 and the base-emitter junction are different, thereby establishing a controlled current through resistor R1 that is independent of temperature.

Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.

Abstract: A deflectable beam spatial light modulator formed from a structure of a reflecting layer, typically metal, on a spacer layer, typically photoresist, which in turn is on a substrate containing electronic addressing circuitry is disclosed. Also, the method of fabrication including a plasma etch after dicing of the substrate into chips is disclosed.

Abstract: A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Abstract: An infrared detector in the form of a focal plane array containing infrared detectors of two sensitivity types is disclosed. The detectors may be based on alloys of HgCdTe with cutoff wavelengths of 5 microns and 10 microns. The two types of detectors are in close proximity and thereby avoid the time delay problem. The two spectral sensitivities make possible the determinaton of spectral signatures and target identification. Further, the two types of detectors are arrayed to permit use of a single set of read lines together with electronic addressing for selecting the detector type, thereby simplifying the output structure and processor design.