Abstract: An efficient pruning method reduces central processing unit (CPU) loading during real time speech recognition by instructing the CPU to compare a current state's previously calculated probability score against a predetermined threshold value and to discard hypothesis containing states with probability scores below such threshold. After determining that the current state should be kept, the CPU is directed to locate an available slot in the scoring buffer where information about the current state is then stored. The CPU locates an available slot by comparing the current time-index with the time-index associated with each scoring buffer slot. When they are equal, the slot is considered not available; when the current time-index is greater, the slot is considered available. After the information about the current state is stored, the CPU then sets the current state's backpointer to point at the start state of the current best path if the current states represents a completed model.

Abstract: A procedure in the formation of semiconductor devices for depositing TiN wherein silane and preferably SiH4 is substituted for the hydrogen in the prior art procedures to provide the approximate twofold to fivefold increase in TiN deposition rate at 400 degrees C. It is believed that the reason for the deposition rate increase is that there is a larger free energy change in the reaction which is believed to occur according to the equation: TiCl4+SiH4+NH3.fwdarw.TiN+SiCl4+(7/2)H2. The above described reaction provides cleaner films when performed in a cold wall CVD reactor than is provided by the prior art procedures as described above. Resistivity of 100 microohm-cm has been measured, this being typical of sputtered TiN films.

Abstract: A column select circuit for a memory device is disclosed which, for unselected data lines, provides a high impedance output. Each data line, and a corresponding decoded address signal, is received by a gate which passes the logic state of the data line (inverted), if selected, to a driver. The decoded address signal is also communicated to the driver, for tri-stating the driver for unselected data lines. The driver consists of a p-channel pull-up and an n-channel pull-down, with an n-channel isolation transistor connected in series therebetween. The driver output is at the junction of the pull-up and isolation devices. The gates of the pull-up and pull-down transistors are connected to the output of the gate, with the gate providing a high logic level when not selected, turning off the pull-up device.

Abstract: The disclosure relates to a wire bonding capillary having a body with a cylindrical upper portion and a contiguous lower tip portion, the tip portion having an exterior inward taper and an internal bore extending through the body, the bore having a first substantially constant cross sectional region extending through the cylindrical portion, a second inwardly tapering region contiguous to the first region, a third substantially constant cross sectional region contiguous to the second region, a fourth outwardly tapering region contiguous to the third region and a fifth outwardly tapered region contiguous to the fourth region having greater outward taper than the fourth region.

Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate.

Abstract: The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Abstract: The described embodiment of the present invention utilizes the regular nature of a large number of arrays by providing a grid scheme in the array to provide a low impedance point to point interconnection. In the described embodiment of the present invention a DRAM includes a number of leads running perpendicular to the sense amplifier layout. For a given signal, each lead is interconnected at a bus lead running parallel to the layout of the sense amplifiers. Thus each lead in the parallel array carries a portion of the current. In addition, in this scheme it can be assured that a substantial number of leads will be near any particular sense amplifier which is drawing on the signal provided on the grid array scheme. Because of the close proximity of the parallel conductors, the bus lines to the sense amplifiers need not be as wide as feeder lines in the prior art.

Abstract: An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.

Abstract: An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

Abstract: A system (10) is provided for etching a surface (14). A vacuum enclosure (12) is provided to create a vacuum around containers (13) and the surface to be etched (14). A pressurized gas source (16) is utilized to input gas into the containers (13). A wire coil (38) is wrapped around the containers (13) and provided with an oscillator (40) to generate radio frequency energy. The radio frequency energy excites the gas within the containers (13) which is then discharged through an output opening (46) toward the surface to be etched (14). A vacuum pump (20) is provided to evacuate the enclosure (12).

Abstract: An adjustable probe to be utilized in probe card technology during the multiprobe electrical testing of integrated circuits. The adjustable probe includes a pair of slots for expansion/contraction and adjustment to obtain a high degree of planarization and placement accuracy of the probe needle.

Abstract: An elastomer connector in combination with a mounting card and retaining part minimizes the distance between tester electronics and the semiconductor device under test and proves a means of adjusting the connector impedance.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The data base is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A semiconductor device for generating tunnel electron carries without a depleted PN junction. A heavily doped P-type semiconductor region (12) is formed in a lightly doped P-type semiconductor substrate (10), and spaced apart from a heavily doped N-type semiconductor region (18), forming a conduction channel (20) therebetween. A thin electrical insulator (14) is formed overlying the P-type region (12) and the conduction channel (20). A gate conductor (16) is formed overlying the thin insulating layer (14). Connections to the semiconductor device are provided by a substrate terminal (22) connected to the substrate (10), a gate terminal (24) connected to the gate conductor (16), and a drain terminal (26) connected to N-type semiconductor region (18). A voltage applied to the gate terminal (24) is effective to cause band bending in the P-type region (12) in excess of the band gap, thereby causing tunneling of electrons from the valence band to the conduction band.

Abstract: Materials for infrared transparent, electrically conductive applications such as gate for infrared detectors made of titanium oxynitride (TiN.sub.x O.sub.y), bismuth, and antimony. Titanium oxynitride with resistivity of at least 0.001 .OMEGA.-cm provides sufficient transmittance for infrared detector gate application as illustrated in FIG. 4.

Abstract: An electrical field-enhanced electron image projector (10) is exposed to an electrical field source (26) to induce the emission of electrons (20) which flow across a gap (28) from a pattern (14) of mask (12) to a photoresist layer (18) of a substrate (16). A heat source (22) can be applied to increase the flow of electrons (20) from the pattern (14) to the photoresist layer (18). As the gap (28) distance decreases, the ability of electrons (20) to move from the pattern (14) to the photoresist layer (18) increases.

Abstract: A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.

Abstract: A power-up 3-state circuit implemented with BiCMOS techniques is described. The circuit disables itself and draws no through current once the operating level of the applied supply voltage is achieved.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A monolithic microwave voltage-controlled oscillator including one or more FETS integrated with a wide-ratio varactor. The varactor includes interdigitated anode and cathode patterns laid out on a single thin epitaxial layer. The punch through voltage of the epitaxial layer, and hence the resistivity-thickness product of the epitaxial layer, must be low. Since the substrate is semi-insulating, punch through to the substrate does not become uncontrollable, but simply permits modulation of the capacitance over a very wide range. The FETS are formed in the same epitaxial layer with the varactor, and complicated doping profiles are not required.