Abstract: A method of interconnecting metal layers in integrated circuits separated by an intermediate dielectric layer by forming first and pillar layers of metal, etching the pillar layer to form a pillar of electrically conducting material and etching the first level to form the first level lead. A layer of dielectric is applied to cover the pillar and first level lead. A layer of photoresist is deposited over the dielectric with a spin on technique to form a planar surface. The dielectric and photoresist are etched back with an equal etch rate until a top portion of the pillar is exposed. A second level lead is formed atop the pillar and planar top surface of the dielectric.

Abstract: An electrostatically deflectable plate spatial light modulator with light reflecting plates (106) composed of aluminum alloy and with symmetrically located supporting hinges (108) connecting the plates (106) to support posts (104); this provides a thick stiff plate and a thin compliant hinges with deflection perpendicular to the plane of the plates.

Abstract: An intelligent multiprobe tip comprising a mounting member comprised essentially of piezoelectric material wherein, through appropriately locating metalized areas, the characteristics of the piezoelectric material are employed to insulate selected regions from each other while providing an appropriate force-induced output signal responsive to the contact of an attached tip with a movable work piece.

Abstract: A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Abstract: A processing apparatus and method wherein two separate gas feeds are provided in proximity to the face of a face down wafer. A shroud can be used to maximize mixing of the two gas feed streams without excessive residence time.

Abstract: A method for passive relative ranging between a position of a moving observer and a stationary remote object includes measuring a plurality of angles at the observer's position to the object from a reference direction at selected or arbitrary time intervals. From the measured angles, calculating the current relative location of the observer with respect to the object, using a non-recursive least square technique employing a Moore-Penrose pseudo-matrix-inverse. The technique is carried out in a general or special purpose digital computer by a program using a predetermined number of variables in which products derived from the measured angles are accumulated, without growth in the number or complexity of calculations with an increasing number of measured angles.

Abstract: A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

Abstract: A cannon launched guided projectile having a gyro based electro-optical target finding and guidance system which includes an optical system carried by a gyro to provide target location information for an electronic system to produce gyro rotor torquing signals and for producing projectile guidance signals from gyro pickoff outputs is disclosed. The electronics system includes two difference channels for processing pitch and yaw signals responsive to the electrical output of a light detector and a sum channel for controlling the two difference channels responsive to target acquisition and master trigger signals.

Abstract: An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).

Abstract: A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor.

Abstract: A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

Abstract: First and second EEPROM cells have first and second source regions (28a, 28b) formed in a semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type of the layer and to be spaced apart from each other. A field plate conductor (100) is insulatively disposed adjacent, and defines, an inversion region (102), and further is laterally spaced between the first and second source regions (28a, 28b). The inversion region (102) is inverted from the first conductivity type to the second conductivity type upon application of a predetermined voltage to the field plate conductor (100). First and second channel regions (48a, 48b) are defined between the respective source regions (28a, 28b) and the inversion region (102) and each include floating gate and control gate subchannel regions (60a, 62a, 62b, 60b). First and second floating gate conductors (40a, 40b) are insulatively disposed adjacent respective floating gate subchannel regions (60 a, 60b) to control their conductance.

Abstract: A void (60) is created in a semiconductor substrate (52) by forming a cavity which is subsequently filled with an organic polymer (66). The organic polymer is masked and etched to form a spacer. A dielectric (70) fills the portions of the cavity where the organic polymer was etched away. The organic polymer is subsequently etched leaving a void.

Abstract: Neural network systems (100) with learning and recall are applied to clustered multiple-featured data (122, 124, 126) and analog data.

Abstract: A BICMOS semiconductor device (20) and method for its fabrication is disclosed. Bipolar, PMOS, and NMOS transistors (22, 26, and 28) are isolated from one another by a P type channel stop (54) implantation step prior to formation of a field oxide (56). An N type channel stop (64) implantation step occurs after the field oxide (56) formation. In addition, the N type channel stop (64) implantation step utilizes the same mask as is used to implant N dopant which forms a deep collector region (62) for the bipolar transistor (22).

Abstract: A vacuum-tight wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The door of the vacuum carrier contains elastic elements to press the wafers lightly against the back of the carrier box. Thus, when the door of the box is closed, the wafers are restrained from rattling around, which further reduces the internal generation of particulates.

Abstract: A visual navigation system provides absolute position information to multiple automatically guided vehicles (AGVs) such as mobile robots. The beacon-equipped AGVs emit light visible to overhead television cameras. The beacons are arranged and controlled so that the vision systems can acquire, measure, and report the locations of multiple AGVs. The system controller incorporates a programmable "factory map", or knowledge base, of allowable paths of travel for the AGVs, which navigate by dead reckoning with periodic position updates from the visual navigation system. The visual navigation system notifies the autonomous AGVs and the system controller when an AGV strays from its command path. The combination of computer controls in the elements of the system provides the means to stop and to recover straying AGVs. The navigation system visually monitors normal AGV travel, off-course corrections, "lost" AGV searches, and recovery. Thus, it provides closed-loop, servo-like operation.

Abstract: A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).

Abstract: A voltage reference circuit (26) provides a stable output reference voltage over a wide temperature range. A high temperature curvature correction circuit (36) is enabled at a first predetermined temperature to adjust the output voltage accordingly. A low temperature curvature correction circuit (38) is enabled at temperatures below a second predetermined temperature to similarly affect a output voltage. The preferred embodiment, the high and low curvature correction circuits (36, 38) are operable to vary the current through one or more resistors in a bandgap circuit (26) or other reference circuit.

Abstract: Disclosed is a small-area solid state driver (30) adapted for switching high voltages. The driver (30) includes a DMOS device (48) driving a bipolar SCR (58). A SCR NPN transistor (54) and PNP transistor (56) are parasitic in nature, thus reducing the wafer area of the driver (30). The SCR (58) provides current sink capabilities to the driver output (60). Current source capabilities are provided by a substrate input terminal (50) which is connected to the output (60) by diodes (84, 86). A third input (52) allows the SCR (58) to be disabled.