Abstract: A CCD imager cell (36, 38) is formed at a face of a semiconductor substrate (10) and has first (36) and second (38) phase regions. A first clocked well (14) is provided for receiving charge integrated in the first phase region (36). A second clocked well (16) is provided for receiving charge integrated in a second phase region (38) adjacent the first phase region (36). A first gate (20) is insulatively disposed over the first clocked well (14), and a second gate (22) is insulatively disposed over the second clocked well (16). A controller controls .phi..sub.1 and .phi..sub.2 pulses such that the charge is transferred from a selected one of the first and second clocked wells (14, 16) to the other, thus integrating all of the charge in the cell into one clocked well thereof. This unified charge is then transferred out from clocked well to clocked well.

Abstract: A system for producing integrated circuit devices includes first and second integrated circuit processing stations. The first station produces an output stream of individual, separate devices for delivery to the second station. A drum buffer receives the individual devices from the first station, selectively stores the individual devices, and dispenses the stored devices on a substantially last-in first-out basis to the second station. The drum buffer includes a plurality of device carrying channels axially along the length of the drum to receive the devices being selectively stored by filling the respective channels as the drum is rotatably indexed in one direction, and to empty the stored devices from the respective channels as the drum is rotatably indexed in an opposite direction.

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: A uniphase, buried-channel, semiconductor charge transfer device wherein a portion of each cell includes an inversion layer, or "virtual electrode" at the semiconductor surface, shielding that region from any gate-induced change in potential. Each cell is comprised of four regions (I, II, III, IV) wherein the characteristic impurity profile of each region determines the maximum potential generated therein for the gate "on" and gate "off" conditions. Clocking the gate causes the potential maxima in regions I and II to cycle above and below the fixed potential maxima in regions III and IV beneath the virtual electrode. Directionality of charge transfer is thereby achieved, since the potential maximum for region II (.phi..sub.max II) remains greater than for region I (.phi..sub.max I) and .phi..sub.max IV>.phi..sub.max III, for both gate conditions.

Abstract: A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: An implantable transponder has a plastic holder having a hollow interior and preferably a rough outer surface, a transmit/receive unit within the hollow interior of the holder, and an electronic element electrically connected to said transmit/receive unit within the hollow interior of said holder. The transmit/receive unit includes a core and coil assembly which may be impregnated with wax, and the hollow interior of the holder is at least partially filled with a plastic filler material such as polysiloxane.

Abstract: Solar spheres are formed of semi-conductor spheres of P-type interior having an N-type skin are pressed between a pair of aluminum foil members forming the electrical contacts to the P-type and N-type regions. The aluminum foils, which comprise 1.0% silicon by weight, are flexible and electrically insulated from one another. The spheres are patterned in a foil matrix forming a cell. Multiple cells can be interconnected to form a module of solar cell elements for converting sun light into electricity.

Abstract: A cache memory addressable by both physical and virtual addresses includes a cach data memory (64) and a tag memory (66). The tag memory (66) is comprised of a virtual tag memory (68) and a physical tag memory (70). The physical and virtual tag memories are both addressable by the least significant bits (LSB) of the address signal to output tag portions of addresses associated with data stored in the cache data memory (64). A switch (78) selects between the outputs from the memories (68) and (70) under control of an arbitration unit (88). The arbitration unit (88) distinguishes between virtual or physical addresses input thereto. A comparator (100) compares the selected tag portion with the tag portion of the received address to determine if a match exists. If a match exists, the output of the cache data memory is selected with a switch (84).

Abstract: A DTMF receiver (10) recognizes each of a plurality of multi-frequency tones, each tone centered on a predetermined standard frequency. Two digital bandpass filters (14, 16) each have four frequency bins, each frequency bin operating according to a recursive second-order transfer function for preferentially transmitting frequencies near the standard frequencies. Each frequency bin accumulates, for each of a plurality of sampling periods, respective spectral energy signals from the input signal. A temporal energy signal is derived from the spectral energy signals. For each bandpass filter (14,16), a time-domain test template generator (30) and a frequency-domain test template generator (34) are provided to generate time-domain and frequency-domain test templates. These test templates are input to an analyzer (38) that compares the templates against data-adaptive frequency-domain and time-domain reference templates.

Abstract: A sense amplifier (10) is provided for with use with a static random access memory. Cascode preamplifier transistors (20a, 20b) convert the complementary currents appearing on bitlines (14a, 14b) coupled to the complementary outputs BIT and BIT of a memory cell (12). The currents are converted into differential voltages and amplified into emitter coupled logic compatible voltages which are output from sense amplifier (10) on DATA line (30a) and DATA line (30b). In a preferred embodiment, a first feedback loop is provided from DATA line (30b) to preamplifying transistor (20a) and a second feedback loop is provided from DATA line (30a) to preamplifier transistor (20b).

Abstract: An amplifier circuit (10) is provided which comprises a first transistor (12) and a second transistor (14). A current buffer circuit (16) is coupled to the basis of the transistors (12, 14) to provide base drive current. A voltage proportional to absolute temperature, V.sub.PTAT, is applied between the emitters of the transistors (12,14). An input current is received by the transistor (12) and an output current is generated by the transistor (14). The output current I.sub.out is amplified with respect to the input current I.sub.in by a gain factor which is substantially independent of temperature considerations. Circuitry is provided for altering the value of the voltage proportional to the absolute temperature, V.sub.PTAT, such that the gain of the amplifier circuit (10) is programmable.

Abstract: A floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage, serves to clamp electrostatic discharge voltages to a low voltage level, thereby minimizing thermal power dissipation within the thin semiconductor layer of semiconductor-on-insulator circuits.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: There is disclosed a fully differential converter (10) having a very high common mode rejection ratio. The capacitive parasitics (CP) are accounted for by a strategic placement of error correction capacitances (20). The actual value of the capacitance is calculated from time to time by successively making comparative circuit operations and by adding and subtracting capacitance automatically under logic control (62) until the circuit is in near balance. The final value of the added capacitance for any given calculation set is stored in a memory (61). In this manner the circuit become self-calibrating and common mode rejection ratios over 90 db are possible.

Abstract: A processing apparatus and method for depositing a silicon oxide layer on a temperature sensitive wafer utilizing a single process chamber provide nitrous oxide gas to the chamber with the excitation energy being provided by a remotely generated plasma while supplying silane gas in combination with illuminating the wafer with an in situ generated ultraviolet energy to produce the silicon oxide layer.

Abstract: A computer memory system for use with a user processor provides automatic memory operations independently of the user processor. The memory system includes a logical memory system which is accessed by the user processor through a binding register unit, enabling the user processor to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The user cannot access the memory directly, but must access the memory through the binding registers. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the user processor.

Abstract: Preferred embodiments include channel stop implants for CMOS devices by through field boron implants (152) after the field oxide (144, 145) has been grown and with the implant depth determined by the thin portions of the field oxide (145). Junction (154) breakdown is preserved by channeling the implant (152) to penetrate far below the junctions (154).

Abstract: A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representastion of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.