Abstract: Substrate support apparatus and methods are described. Motion of a substrate chuck relative to a stage mirror may be dynamically compensated by sensing a displacement of the substrate chuck relative to the stage mirror and coupling a signal proportional to the displacement in one or more feedback loops with Z stage actuators and/or XY stage actuators coupled to the stage mirror. Alternatively, a substrate support apparatus may include a Z stage plate a stage mirror, one or more actuators attached to the Z stage plate, and a substrate chuck mounted to the stage mirror with constraints on six degrees of freedom of movement of the substrate chuck. The actuators impart movement to the Z stage in a Z direction as the Z stage plate is scanned in a plane perpendicular to the Z direction. The actuators may include force flexures having a base portion attached to the Z stage plate and a cantilever portion extending in a lateral direction from the base portion.

Abstract: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: Targeted sound detection methods and apparatus are disclosed. A microphone array has two or more microphones M0 . . . MM. Each microphone is coupled to a plurality of filters. The filters are configured to filter input signals corresponding to sounds detected by the microphones thereby generating a filtered output. One or more sets of filter parameters for the plurality of filters are pre-calibrated to determine one or more corresponding pre-calibrated listening zones. Each set of filter parameters is selected to detect portions of the input signals corresponding to sounds originating within a given listening zone and filter out sounds originating outside the given listening zone. A particular pre-calibrated listening zone is selected at a runtime by applying to the plurality of filters a set of filter coefficients corresponding to the particular pre-calibrated listening zone.

Abstract: Voice recognition methods and systems are disclosed. A voice signal is obtained for an utterance of a speaker. A runtime pitch is determined from the voice signal for the utterance. The speaker is categorized based on the runtime pitch and one or more acoustic model parameters are adjusted based on a categorization of the speaker. The parameter adjustment may be performed at any instance of time during the recognition. A voice recognition analysis of the utterance is then performed based on the acoustic model.

Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

Abstract: Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions, are executed based on a first clock (which may be a fixed clock) and the translated instructions are executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.

Abstract: A measuring device incorporating a substrate with sensors that measure the processing conditions that a wafer may undergo during manufacturing. The substrate can be inserted into a processing chamber by a robot head and the measuring device can transmit the conditions in real time or store the conditions for subsequent analysis. Sensitive electronic components of the device can be distanced or isolated from the most deleterious processing conditions in order increase the accuracy, operating range, and reliability of the device. Isolation may be provided by vacuum or suitable material and phase change material may be located adjacent to electronics to maintain a low temperature.

Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs.

Abstract: A fluidic optical device, systems utilizing fluidic optical devices, methods for manufacturing fluidic optical devices and actuators are disclosed.

Abstract: An optical method and system for measuring characteristics of a sample using a broadband metrology tool in a purge gas flow environment are disclosed. In the method a beam path for the metrology tool is purged with purge gas at a first flow rate. A surface of the sample is illuminated by a beam of source radiation having at least one wavelength component in a vacuum ultraviolet (VUV) range and/or at least one wavelength component in an ultraviolet-visible (UV-Vis) range. A flow rate of a purge gas is adjusted between the first flow rate for metrology measurements made when the source radiation is in the VUV spectral region and a second flow rate for metrology measurements made when the source radiation is in the UV-Vis spectral region. The system includes a light source, illumination optics, collection optics, detector, a purge gas source and a controller.

Abstract: The capabilities of the Modulated Optical Reflectance (MOR) technology in dopant metrology applications are combined with the sensitivity of the PhotoReflectance (PR) method in the present system to provide stress and other measurements in semiconductor samples. Such combination enhances the measurement performance of MOR based systems in ion implant applications (implantation dose and energy) and expands system capabilities into a new area of structural parameters measurements, for example, strain in silicon wafers.

Abstract: Switching optical signals containing a plurality of spectral channels characterized by a predetermined channel spacing is described. A selected beam deflector array may be selected from among a plurality of available beam deflector arrays configured to accommodate spectral channels of different channel spacings. The selected beam deflector array is configured to accommodate spectral channels of the predetermined channel spacing. The spectral channels are selectively optically coupled to the selected beam deflector array, which selectively optically couples the spectral channels between one or more input ports and one or more output ports.

Abstract: A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad.

Abstract: Secure operation of cell processors is disclosed. A cell processor receives a secure file image from a client device at a cell processor of a host device (host cell processor), wherein the secure file image includes an encrypted SPU image.

Abstract: A method for processing of processor executable tasks and a processor readable medium having embodied therein processor executable instructions for implementing the method are disclosed. A system for distributing processing work amongst a plurality of distributed processors is also disclosed.

Abstract: A method and system for performing measurements on a test sample with a metrology or inspection tool are disclosed. At least one of the test sample and the tool is moved with respect to the other from a first position to a second position. At the second position, the tool is aligned for measurement of a measurement target on the sample. A focus of the tool on the test sample is adjusted while moving from that first position to the second position.

Abstract: Some problems related to processing workpieces are presented along with solutions to one or more of the problems. One embodiment of the invention comprises a sensor apparatus for collecting data representing one or more process conditions used for processing a workpiece. Another embodiment of the present invention is a combination comprising a sensor apparatus and a process tool for applications such as chemical mechanical planarization of workpieces and chemical mechanical polishing of workpieces.

Abstract: A method and system for semiconductor wafer inspection is disclosed. Each of a plurality of dies on a wafer may be probed with a probe tool to produce probe data. The probe data may be used to generate one or more non-repeating care areas. An inspection tool may use the non-repeating care areas to perform an inspection of the semiconductor wafer.