Abstract: Lost frame reconstruction is described. A previous good or reconstructed frame may be analyzed to determine a category for the lost frame. A percentage Pi may be associated with the determined category of the lost frame. A top Pi percent magnitude samples may be zeroed out in an excitation of the previous good or reconstructed frame to produce a reconstruction excitation. The reconstruction excitation may be applied to one or more linear prediction coefficients for the previous good or reconstructed frame to generate a reconstructed frame.

Abstract: A system and method for routing communications among real and virtual communication devices are disclosed. The system includes one or more processors configured to generate a virtual world. The one or more processors may be configured to generate a virtual communication device and implement a configurable router adapted to facilitate routing of a communication among one or more real communication devices and the virtual communication device. A user of the virtual world may be associated with a virtual communication device and one or more real communication devices. A routing preference for reception of communications targeted to the user is implemented among the virtual communication device and the one or more real communication devices.

Abstract: A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/or data for a second context in a second region of the local memory, the secondary processor may execute the first context while the second context waits. Code and/or data for the first context may be transferred from the first region to the second and code and/or data for the second context may be transferred from the second region to the first, and the processor may execute the second context during a pause or stoppage of execution of the first context. Alternatively, the code and/or data for the second context may be transferred to another processor's local memory.

Abstract: A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”.

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract: Methods and apparatus for parallel processors are disclosed. A policy module is loaded from a main memory of a processor into the local memory of a selected secondary processing element under control of a policy module manager running on the secondary processing element. A selected one or more work queues are assigned from a main memory to a selected one or more of the secondary processing elements according to a hierarchy of precedence. A policy module for the selected one or more work queues is loaded to the selected one or more secondary processing elements. The policy module interprets the selected one or more of the selected one or more work queues. Under control of the policy module, work from one or more of the selected one or more work queues is loaded into the local memory of the selected secondary processing element. The work is performed with the selected secondary processing element.

Abstract: Use of runtime memory may be reduced in a data processing algorithm that uses one or more probability distribution functions. Each probability distribution function may be characterized by one or more uncompressed mean values and one or more variance values. The uncompressed mean and variance values may be represented by ?-bit floating point numbers, where ? is an integer greater than 1. The probability distribution functions are converted to compressed probability functions having compressed mean and/or variance values represented as ?-bit integers, where ? is less than ?, whereby the compressed mean and/or variance values occupy less memory space than the uncompressed mean and/or variance values. Portions of the data processing algorithm can be performed with the compressed mean and variance values.

Abstract: A sensor apparatus for measuring a plasma process parameter for processing a workpiece. The sensor apparatus includes a base, an information processor supported on or in the base, and at least one sensor supported on or in the base. The at least one sensor includes at least one sensing element configured for measuring an electrical property of a plasma and at least one transducer coupled to the at least one sensing element. The transducer is configured so as to receive a signal from the sensing element and converting the signal into a second signal for input to the information processor.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: A device has a metal wireframe with two lateral fastening elements which are connected through metal lingual and vestibular springs to a frontal fastening element and executed in the form of metal wireframes clasping teeth of dentition's lateral segments and performed of lingual and vestibular details located at necks of teeth from the one side and dispersedly mounted along the height of teeth from the other side and connected by crosspieces.

Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Abstract: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

Abstract: Methods and apparatus for entropy decoding are disclosed. Compressed input data representing one or more signals is loaded into one or more registers. A first candidate value for a most probable signal case is prepared from the input data. A second candidate value for a least probable signal case is prepared from the input data. A final signal value for the one or more signals is selected from the first and second candidate values and an output bin value is generated based on the final signal value. A processor readable medium having embodied therein processor readable instructions for implementing the method for entropy decoding is also disclosed. In addition, a method of avoiding a branch instruction in an electronic processing algorithm is disclosed.

Abstract: Real-time simulation of liquids is disclosed. A liquid may be modeled as a collection of particles. Particles separated from one or more nearest neighbor particles by a distance greater than a threshold distance may be separated out as droplets. An iso-surface may then be determined and rendered for the particles not separated out as droplets. The droplets may be rendered as sprites.

Abstract: A method and apparatus for software development and a method and system for analysis of graphics software are disclosed.

Abstract: A fluidic lens may have a transparent window member, a transparent distensible membrane, an inner ring between the window member and membrane, and a top ring disposed such that the membrane is between the piston ring and the inner ring. A layer of liquid may be stored between the window member, the inner ring and the membrane. The top ring may be adapted to apply a liquid displacement force to the membrane in a direction perpendicular to a plane of an aperture of the inner ring to cause a change in a radius of curvature of the membrane. The membrane may be pre-tensioned prior to assembly with the other components.

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract: A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.

Abstract: A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.

Abstract: Methods and apparatus for facilitating traversal of a network address translator (NAT) are disclosed. For example, a node configured to communicate with one or more other nodes over a network may facilitate NAT traversal by a) determining information regarding the behavior of one or more NATs with the node; and storing the information in such a way that the information is retrievable by one or more other nodes; or b) retrieving information regarding behavior of one or more NATs obtained by one or more other nodes and using the information to traverse one or more of the NATs.