Abstract: A configurable cellular array is provided having a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least one bit wide to its neighbours. Each cell also has a programmable routing circuit to permit intercellular connections to be made. In one arrangement each cell contains a programmable function unit which includes a plurality of multiplexers. In a preferred arrangement the function unit and routing unit are programmable using associated Random Access Memory (RAM) areas within the cell. Each cell may be coupled to at least one global or array-crossing-signals so that all cells can be signalled simultaneously. The 2-dimensional array is rectangular and the intercell connections are orthogonal and are one bit wide.

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Abstract: A programmable interconnect is provided that includes a first plurality of lines, a second plurality of lines, and means for connecting one of the first plurality of lines to one of the second plurality of lines, wherein the means for connecting includes an antifuse and a diode. The diode in this configuration performs the equivalent logical function as an AND gate. Programing the antifuse determines the diode-AND gate function performed. In this manner, a programmable interconnect array in accordance with the present invention, formed using standard fabrication processes, provides an area-efficient implementation of a wide AND functionality.

Abstract: An antifuse for programmable integrated circuit devices is formed above a refractory metal on a thin native oxide layer and comprises an amorphous compound resulting from an PECVD deposition using a combination of silane gas and nitrogen. After formation of the amorphous antifuse layer, the layer is implanted with an atomic species such as argon. The thin oxide layer is formed on the surface of a refractory metal, therefore the process of forming the oxide is slow, the oxide is of even thickness, and the thickness can be controlled precisely. In a preferred embodiment, a second thin oxide layer is formed above the doped amorphous layer. The oxide layers significantly reduce the leakage current of an unprogrammed antifuse. Because of these thin oxide layers and the implantation step, the amorphous layer may be as thin as 200 .ANG..

Abstract: A carry-lookahead structure for programmable architectures includes a number of M-bit carry lookahead units, each M-bit unit having two parallel programmable carry paths having AND gates controlled by configuration bits to program the beginning and end of an operating carry chain within the M-bit units, as well as the beginning locations in each unit, one path generating a first set of carry bits for the case of the carry-in equal to 0, and the other generating a second set of carry bits for the case of the carry-in equal to 1, and at least one multiplexer controlled by the carry-in for selecting one of the two carries at the most significant bit of the first and second sets of carry bits as carry-out of the unit. Each M-bit unit may further include multiplexers controlled by the carry-in for selecting which of the first and second sets of carry bits are the correct carry bits for addition and M sum logic elements for generating the outputs of sum bits.

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract: A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position.

Abstract: A computer aided design system for electronic digital circuitry allows the circuit designer to design a circuit using high level block components, The designer specifies data type and precision (bus width) parameters as desired for whichever circuit blocks and/or busses he desires, Then the system propagates the data types and precision throughout the design automatically to achieve circuit-wide consistency, The system can also be used to verify a circuit design for data type and bus width consistency, The system can also be used to determine the mode of operation for the circuit blocks in the circuit.

Abstract: A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter.

Abstract: The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.

Abstract: A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

Abstract: A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed. Once again, the wafer is subjected to adverse conditions.