Abstract: A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal.

Abstract: A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position.

Abstract: Logic is represented in a schematic capture program as a generic symbol. The generic symbol represents a single underlying logic circuit, thereby decreasing library space. The generic symbol includes a configuration memory which is represented on the symbol by a plurality of pins. The generic symbol is configured by indicating the logic signals placed on the plurality of pins. In this manner, the generic symbol significantly increases the design choices available to the end user. Moreover, the generic symbol allows access to the underlying logic of the circuit via the selected bit pattern, thereby advantageously permitting the end user to perform functional simulation within the schematic environment. In one embodiment, a plug symbol is provided to schematically connect to the generic symbol. This plug symbol represents a predetermined pattern of bits, thereby significantly simplifying configuring the logic in the schematic capture program.

Abstract: A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a sequential logic element, wherein at least one programmable logic element includes a plurality of memory cells for configuring the combinational element and at least one programmable logic element includes a plurality of memory cells for configuring the sequential logic element. A micro register, which stores a plurality of intermediate states of one CLB or interconnect structure, is located at the output of a CLB, the input of a CLB, or elsewhere in the interconnect structure. The PLD includes means for disabling access to at least one of said plurality of memory elements. In one embodiment, the memory cells are RAM cells, whereas in other embodiments the memory cells are ROM cells, or a combination thereof.

Abstract: A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.

Abstract: A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Abstract: A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase.

Abstract: A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Abstract: A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element.

Abstract: In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

Abstract: A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0.

Abstract: A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.

Abstract: A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.

Abstract: A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock.

Abstract: A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

Abstract: A programmable logic device (PLD) includes at least one configurable element, a plurality of programmable logic elements for configuring the configurable element(s), and a sequencer coupled to the plurality of programmable logic elements. Each programmable logic element typically includes a plurality of memory cells, wherein the sequencer accesses one of the plurality of memory cells during one step in a sequence of steps, each step initiated by one or more trigger signals. If the sequencer receives a plurality of trigger signals simultaneously, then the sequencer prioritizes these signals. Generally, each step provides one configuration of the PLD. In one embodiment, the sequence of steps includes less than all configurations of the PLD. In another embodiment, one trigger signal initiates a plurality of sequences of configurations.

Abstract: A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line.

Abstract: A plurality of DRAM cells are used to store the state of the programmable points in the FPGA ("FPGA DRAM cells"). A shadow DRAM array holds duplicate data of the plurality of DRAM cells. A DRAM cell of the shadow DRAM array is sensed during a refresh cycle. In this manner the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.

Abstract: A synchronization mechanism for synchronizing an outside clock with a delayed inside clock is provided. The delayed inside clock is distributed across a network of clock lines within the integrated circuit to deskew the clock signal at the supply points. Although the inside clock signal is deskewed, it is nevertheless delayed compared to an input clock signal provided by a pad of the integrated circuit. A distribution line provided on the periphery of the integrated circuit supplies an outside clock signal that is not substantially delayed compared to the input clock signal at the IC's pad. The synchronization mechanism provides synchronization between the outside clock, as received by an input/output block, and the inside clock. The synchronization is required because configurable logic blocks (CLBs) of the IC are typically referenced by the delayed inside clock.

Abstract: According to the invention, a regulated voltage pump is provided which uses a chain of diodes between each of which is attached one plate of a capacitor for which the other plate is driven by a clock signal. The regulated voltage pump of the present invention uses feedback from the output signal to determine how many capacitors to pump. A comparator compares a signal related to the pumped output signal to a reference voltage (which may be the power supply voltage) and controls how many intermediate pumping capacitors receive a switching clock signal. Thus a regulated pumped voltage is provided.