Abstract: An antifuse functions as a resistive element in an SRAM cell. The antifuse layer, typically amorphous silicon, is formed to a thickness commensurate with the resistance required for proper functioning of the SRAM cell. The antifuse load SRAM cell of the present invention advantageously reduces chip area and simplifies the fabrication process. Specifically, the formation of the amorphous silicon layer is an easily controlled parameter which is therefore easily reproducible. Moreover, antifuse processing is compatible with standard CMOS processing.

Abstract: A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Abstract: A method of providing placement information during design entry is described which includes the steps of indicating an element type in an instance, identifying a port list for a specific element in the instance, and providing embedded placement information regarding the specific element in the instance. In one embodiment, the embedded placement information includes a cell location, whereas in another embodiment, the embedded placement information includes a block location. This method eliminates the need for a separate file with placement information, thereby improving user efficiency and significantly minimizing user error.

Abstract: A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources. Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables. If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements.

Abstract: The multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier and outputs a M+N bit product. The multiplier circuit includes a number of recoder circuits. The recoder circuits recode the N bit multiplier into fewer bits, thereby reducing the longest signal path through the multiplier circuit and increasing the speed of the circuit. In one embodiment, the recoder circuits perform a N to N/2 Booth recoding. The recoder circuits are combined with other circuitry to generate partial products. The partial products are combined in a three to two compression circuit. The compression circuit further reduces the longest signal path through the multiplier circuit. In one embodiment, the three to two compression circuits are configured in a Wallace Tree. In another embodiment, four to two compression circuits are used. The compression circuit outputs two addends. The two addends are then added in an adder to generate the product.

Abstract: A configuration emulation circuit generates configuration signals to emulate a programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect crossover.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip.

Abstract: An interface assembly in the present invention includes a plate for mounting a test head, a plurality of alignment pins for aligning the test head to a device including a plurality of compressible pins, and a plurality of vacuum-activated components for coupling the plate to the device. After the test head is positioned in operative relation to the other device, the vacuum-activated components provide a vacuum which draws the plate and the device together. The interface assembly eliminates the purely mechanical securing of the plate to the device, thereby minimizing any rocking of the test head and ensuring equal compression of the plurality of compressible pins. The interface assembly also ensures safe user operation by providing that any obstacle (such as a user's finger) between the interface assembly and the device prevents creation of a vacuum. Thus, the present invention provides a time-efficient, reliable, safety-conscious means for positioning a test head relative to another device.

Abstract: An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion.

Abstract: The more highly integrated programmable circuits include several kinds of resources for implementing the user's logic diagram. The resources provided in the chip hardware are intended to implement functions commonly specified by a user, in order for a complex chip to efficiently implement a complex design, the features called for in the design must be matched with the resources offered in the chip hardware. The present invention evaluates a user's logic diagram in comparison to resources available on a particular chip and matches a plurality of features in the design to resources in the chip which can efficiently implement those features.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources.

Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Abstract: A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU.

Abstract: Propagation delay along a signal path in a programmable logic device is reduced by providing improved switching and buffering along the device signal path. Such improvement is achieved by providing a separate buffer for each signal path leading from a given device input pad. In this manner, the buffer is smaller without increasing net power consumption. Improved output drivers are also provided in which device sizes are optimized to sink/source larger amounts of current, thereby improving device speed. A feedback arrangement, including a bootstrap device, provides a path that augments the current provided within the output buffer, thereby assisting a low to high signal transition. An improved OR gate is also provided that precharges a gate output line to ensure fast state transition, while eliminating the need for complementary gate switching logic.

Abstract: In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V.sub.GG level, where V.sub.GG .gtoreq.V.sub.DD +V.sub.TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V.sub.GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Abstract: A memory system and method which allows a plurality of memory circuits to be operated independently as separate memories, or jointly as a single memory. Alternatively, the selected memory circuits are operated jointly and other memory circuits are operated independently. The configuration of the memory system can be varied dynamically during operation of the memory system.

Abstract: A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with the highest priority (wherein M is the number of real LUTs in the PLD), labeling the M LUTs with the current micro cycle number, removing the M LUTs from the list, identifying the next micro cycle, and if labelled LUTs exist, then repeating all steps, otherwise exiting the computer-implemented method.

Abstract: A system for interfacing with a test access communication port. Specifically, the present invention has application to the IEEE 1149.1 Test Access Port ("JTAG") standard. The novel system includes a hardware unit having a memory unit and a special processor unit (SPU) that interfaces between the test access port and components of a general purpose host computer system. The host computer system uses software procedures to formulate a set of compressed instructions instructing the hardware unit to generate and/or receive signals in connection with the test access port. In one embodiment, the host computer system contains configuration data in a special format. The host computer system translates this configuration data into the compressed instructions which are transmitted to the hardware unit causing it to download the configuration data using signals recognized by the test access port. The data is downloaded into a programmable integrated circuit device using the test access port.