Abstract: A method and apparatus for dynamically varying the impedance of a tank circuit whereby, over time, the response of the circuit to a received signal is maximized.

Abstract: The invention describes a method and device for designing a set of codewords, which have good properties for use in communication systems. These codeword sets are useful because they provide advantages to a communication system that uses them in that they result in lower error rates in the receiver. The method for designing the codes is to take a good set of codes with perfect periodic autocorrelation and manipulate it so as to transform it into a better code-set, for example a code-set with higher mean Golay merit factor, lower spectral peak to average ratio and lower mean cross correlation.

Abstract: A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

Abstract: A method and apparatus for transmitting and receiving convolutionally coded data in a communication system employing a combination of Pulse Position Modulation (PPM) and Binary Phase Shift Keying (BPSK), wherein the code is selected to have error rate performance that is as good as the best convolutional code used with systems employing only BPSK.

Abstract: A method and apparatus for dynamically varying the impedance of a tank circuit whereby, over time, the response of the circuit to a received signal is maximized.

Abstract: In a digital data processing system having an on-line file system component, a method and apparatus for archiving the contents of a selected client volume stored on the file system. The archiving is performed automatically, beginning with an initial duplication of the existing contents of the client volume into an archive volume, then continuing as changes, including additions, deletions and modifications, are made to the files comprising the client volume. Older, previously-archived versions of modified files are gracefully discarded so as to moderate the rate of growth of the archive volume. The archive volume may be used to restore the client volume, either selectively or in whole, in the event of inadvertent damage to, or loss of, files in the client volume.

Abstract: A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examined by the FireBreak to determine if they violate any of a plurality of protection rules stored in a local protection rules database. Any transaction found to be in violation is discarded. Valid transactions are forwarded to the BlackNet. If an otherwise valid transaction is found to be suspicious, the FireBreak will forward to a FireNet Server relevant information relating to that transaction. If the FireNet Server verifies that the transaction is indeed part of an attack, the FireNet Server will create new protection rules suitable to defend against the newly identified source or strategy of attack. Periodically, all FireBreaks in the FireNet system will transfer, directly or indirectly, all new rules.

Abstract: A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

Abstract: A method for managing tasks in a data processing system having a shared task, which may be performed in hardware, software, or a combination of both. In response to a request from a requesting task, the task manager of the data processing system initiates performance of the shared task on behalf of the requesting task. At selected points in the performance of the shared task, the requesting task may cooperate with the shared task to selectively store watchpoints, each comprising sufficient information about the then-current status of the shared task to allow resumption of that task. During the performance of the shared task, the requesting task can determine if the shared task is still performing that task on behalf of the requesting task.

Abstract: An apparatus for operating a dynamic memory (11) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller (112) accesses a look up table (106) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler (122). In one embodiment, the background value is written to the inactive memory cell (152) via sense amplifier killer circuitry (154).

Abstract: A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

Abstract: A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).

Abstract: A method for operating a dynamic memory (11) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller (112) accesses a look up table (106) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler (122). In one embodiment, the background value is written to the inactive memory cell (152) via sense amplifier killer circuitry (154).

Abstract: A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO.

Abstract: In one embodiment, a plurality of atomic charge pumps (52, 54, 56) are connected together in series to form a distributed charge source (24). The atomic charge pumps (52, 54, 56) are operated sequentially over time to reduce supply signal noise. In addition, the distibuted charge source (24) is compatible with low power applications because each atomic charge pump (52, 54, 56) can be independently powered down if it is not required.

Abstract: A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c′, 32c″).

Abstract: An extensible central processing unit (CPU) (12 or 12'). By modifying the architecture of a new or prior art CPU, a new or prior art CPU can be made extensible so that new instructions can be added in a simple and cost effective manner to meet differing customer needs. The term "extensible" in regard to a CPU is used to mean that new instructions can be added to the CPU simply by adding certain designated circuitry, without the need to significantly change the existing CPU circuitry. In some embodiments, the additional designated circuitry may include control circuitry in the form of CPU control extension circuitry (52 or 152). In some embodiments, the additional circuitry may include non-control circuitry in the form of execution unit extension circuitry (153).

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.