Abstract: A modulo arithmetic unit for providing a sum or difference of two numbers of arbitrary value in a selected one of a plurality of moduli is provided. Each modulus has a lower and an upper boundary and a range of intermediate values. First and second adders are provided for respectively providing first and second outputs which respectively represent outputs compensated for and not compensated for a possible wraparound of the upper or lower boundary. Control circuitry is used to detect whether a wraparound occurred during the calculation depending upon the value of selective interstage carry signals of the first and second adders. The correct output is provided as a selected one of the outputs of the first and second adders in response to the control circuitry.

Abstract: A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

Abstract: A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when the inputs are at a voltage intermediate a power supply voltage. Prior to the pair of bit lines being coupled to the data line pair, the data lines are biased to the intermediate voltage which is in the range of maximum gain of the secondary amplifier so that the secondary amplifier will operate at maximum gain which results in increased speed of operation of the dynamic random access memory.

Abstract: A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.

Abstract: A process for selective deposition of a refractory metal such as tungsten at high temperatures and low pressure via chemical vapor deposition during semiconductor device manufacturing is provided. A dielectric layer is nitrided by chemical deposition of a nitrogen bearing gas prior to LPCVD deposition of tungsten for purposes such as contact metallization of current conducting electrodes and current controlling electrodes of transistors. Since nitridation of the dielectric is a surface chemical reaction and not an addition of material to the dielectric, no additional complexity is introduced into the LPCVD process. The refractory metal does not substantially deposit on the nitrided dielectric thereby providing selective metal deposition.

Abstract: A method which reduces the memory required to store correction factors used in logarithmic addition and subtraction of logarithmic operands. The method is implemented by a circuit which adds a predetermined correction factor to the minimum value of two logarithmic input operands. Correction factors are quantized to single polarity values. Predetermined ranges of magnitude values of the correction factors are selected in which the minimum value of each range is represented by a bias level. As a result of the bias levels, stored representations for the addition and subtraction factors are made much smaller resulting in less memory which is required. An addition of a predetermined bias level to the minimum value is effected simultaneous to addressing a predetermined adjustment factor in the reduced memory. A second addition is required to provide an output which represents either an addition or subtraction of the signed operands.

Abstract: A power amplifier particularly useful as a line driver operating at low power supply voltages is provided. An input portion comprising a differential input configuration is coupled to an output stage having a P-channel MOS transistor connected in series with an N-channel MOS transistor between two power supply voltage terminals. A control portion is coupled to both the input portion and the output stage for providing first and second control signals to the output portion. The control portion regulates the output quiescent current at a predetermined value independent of signal amplification provided by the input portion. The output signal can swing substantially between two power supply voltage potentials.

Abstract: A circuit for receiving a plurality of signed operands which each represent an exponential value to a predetermined base and for selecting one of the operands which results in a maximum value is taught. The circuit has a rank ordered plurality of logic circuits which each receives a predetermined bit of each operand and provides an output bit of the maximum value. The output of the logic circuits is a transcoded output which is a translation value of the maximum value. A sign control circuit receives a sign bit of each signed operand and controls the operation of the logic circuits in response to the values of the input operands.

Abstract: A process for removing the edge bead of films that are spun onto a planar substrate, which edge bead collects at the edge of the substrate. In processes such as the manufacture of integrated circuits, the edge bead of brittle substances such as glass, SiO.sub.2, tends to shatter upon subsequent high temperature processing and generates particles which contaminate further processing of the integrated circuits. A pulsed or repeated application of a solvent on the edge of the substrate, a backwash step of constant rotational speed and a deceleration over time provides a means of smoothing and gradual cutting back of the spun on film edge. The deceleration spin has a starting rotational speed and a final rotational speed; and the subsequent backwash step is always at a constant rotational speed lower than the starting speed of the previous deceleration spin.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: A process having three steps to etch a vertical trench with rounded top corners and rounded bottom corners. The first step involves anisotropically etching a vertical trench through an opening in a masking layer to approximately 85 to 90% of the final trench depth to give a trench with sharp or abrupt top corners and sharp bottom corners. The second step rounds the top corners and the third step extends the trench depth and provides rounded bottom corners. Using CHF.sub.3 as an etch species and adjusting the DC bias differently for each step gives better profile control and better critical dimension (CD) control.

Abstract: An isolation formation process that minimizes bird's beak encroachment and preserves gate oxide integrity in the active region. Future active areas are protected by a structure having a central protective material layer, such as a thermal oxide, surrounded by a ring of thermal nitride. The thermal nitride and central protective material are coated by active region protection masking covers. In one embodiment, the masking covers include sidewalls over the thermal nitride ring. In another embodiment, the central protective material layer is overetched beneath an undercut covering layer to provide an undercut filled by the sidewall. All of these features contribute to bird's beak encroachment prevention which may be narrowed to as little as 0.07 microns per side.

Abstract: A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.

Abstract: A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range.

Abstract: In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.

Abstract: A clock generator is used in a non-volatile memory to generate a timing signal for clocking a sense amplifier. The timing signal duration is timed using circuit features which also affect the rate with which data can be sensed by the sense amplifier. The clock generator includes a reference word line which is analogous to an accessed word line, a memory cell which establishes a reference current analogous to that provided by an accessed cell, and a current mirror which uses the reference current to charge a reference line analogous to a bit line. The duration of the timing signal is established by the reference line reaching a predetermined voltage.

Abstract: A redundant decoder for use in a predecoded memory scheme includes a plurality of predecoding circuits each having an output and each having inputs coupled to selected address signals. The outputs of the predecoding circuits are applied to the inputs of a smaller group of decoding circuit. In addition, the outputs of the predecoding circuits are coupled to the gate electrodes of one of a plurality of series coupled field effect transistors each having a laser blowable fuse coupled across its source drain path. Should one of the decoding circuits prove to be operating improperly, is only necessary to blow the fuses across the individual field effect transistors whose gate electrodes are coupled to the predecoding circuit outputs which served as inputs to the bad gate. In this manner, the output of the stack will go high only when the output of the bad decoding circuit should go high.

Abstract: An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.