Abstract: An EEPROM has two arrays which provide data in response to an address. The EEPROM can be programmed to function in one of two modes. The EEPROM can supply data from a selected one of the arrays or can simultaneously supply data from both arrays. In the mode in which data is supplied simultaneously from both arrays, the data from both arrays is coupled to a common data line where the data is sensed by a sense amplifier.

Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

Abstract: A quick-release multiple gas injection pipe connector fitting for removable attachment to a gas reaction chamber having a plurality of gas injection passages. The fitting permits a number of gas inlet lines to be removed from or attached to a reaction chamber fixture in one operation without a separate removal or attachment step for each gas line. The fitting also facilitates a process where the reaction gases are preferably mixed only at the reaction site and not before.

Abstract: A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface regions and a spacer forming material is deposited over the electrodes and the surface regions. The spacer material is anisotropically etched from one of the surface regions to form spacers at the edge of the first gate electrode while retaining the spacer forming material over the second surface region. Source and drain regions of the first MOS transistor are implanted using the spacers as an implantation mask. The spacers are removed and a lightly doped source and drain is implanted using the gate electrode as a mask. The implanted source and drain regions are oxidized using the remaining spacer forming material as an oxidation mask to prevent oxidation of the second surface region.

Abstract: An arithmetic logic unit capable of performing AND, OR, exclusive-OR, and add functions is implemented utilizing strobed gates. An input section receives first and second inputs, each capable of assuming first and second states, and generates a first output indicating that at least one of the inputs is in a first state and a second output indicating that both inputs are in the first state. First, second and third strings of field-effect-transistors controlled by a plurality of control signals are selectively enabled respectively when at least one of the inputs is in the first state, all of the inputs are in the first state, or when only one of the inputs is in the first state. The circuit includes an output section and a circuit for generating a carry-out signal when the inputs so require.

Abstract: A single-chip microcomputer comprises at least two separate and independent electrically erasable programmable read only memories (EEPROMs) on-board which may be independently programmed, erased and read. Each part of the split EEPROM has its own data bus and address bus. Programming and erasing is controlled by a program register which has separate bits for configuring and latching the data and address buses of a selected EEPROM array, for providing programming voltage to the array of choice and for choosing between programming and erasing the selected array. The split EEPROM provides versatility to the user in allowing one part of the EEPROM to be programmed while the program stored in another part of the EEPROM or RAM may be read and utilized. In addition, test time and effort of the microcomputer may be considerably reduced.

Abstract: A dynamic random access memory, formed in a substrate, has an array comprised of intersecting rows and columns with memory cells at intersections thereof. Along each row is a plurality of memory cells. Each memory cell has a storage capacitor and a transfer device. The transfer device is a transistor which has gate to which is applied a voltage to select the memory cell. Each transfer device has an insulator between the its gate and the substrate. During a test mode of the memory, all of the transfer gates are subjected to a stress test of this insulator to provide an accelerated test for the integrity of this insulator.

Abstract: An erase circuit for an EEPROM is provided which only uses enhancement type transistors. This eliminates having to use additional processing steps to provide depletion type transistors in a CMOS process. Enhancement type transistors are used to provide the erase voltage to the control gate of an electrically erasable memory cell. An additional enhancement type transistor is used to maintain the control gate in a non-floating condition during non-erase periods.

Abstract: A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.

Abstract: Two state machines, each active during a respective one of two complementary non-overlapping clock phases, are interlocked so that the present state of one machine determines the next state of the other machine, and vice versa.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: An input protection circuit is provided which prevents positive and negative voltages significantly higher than a supply voltage potential from damaging operational circuitry connected to an input terminal. A bipolar transistor has current conducting electrodes connected between the supply voltage and the input terminal. A first MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and collector of the bipolar transistor in response to the sign and magnitude of an input signal. A second MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and emitter of the bipolar transistor in responses to the sign and magnitude of the input signal.

Abstract: An improved process is disclosed for forming the field oxide which provides isolation between adjacent devices in an integrated circuit. In one embodiment of the invention the improvement includes implanting halogen ions, and preferably chlorine ions, into the selected regions of a semiconductor substrate where field oxide is to be formed. The halogen ions are implanted before the field oxide is thermally grown and result in a localized enhancement of the oxide growth rate in the vertical direction compared to the lateral direction. For a given oxidation cycle, the halogen implant results in the growth of a thicker oxide with minimum lateral encroachment.

Abstract: In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

Abstract: A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.

Abstract: A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

Abstract: In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.