Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: Status flag handling method and apparatus for use in a digital data processing system provide error-resistant operation and simplicity. Two storage elements comprising one bit of a status register are operated such that: a reset places both elements in first predetermined states; a set flag operation places both elements in second predetermined states; a read flag operation alters the state of the second storage element; and a clear flag alters the state of the first storage element if and only if the state of the second storage element has previously been altered by a read flag operation. The flag output corresponds to the state of the first storage element. When implemented with single instructions, inadvertant flag negation and errors due to intervening interrupts are avoided. The read flag operation temporarily disables the set flag mechanism, protecting against setting the flag during a read operation. The flag is always read as asserted prior to being negated.

Abstract: A cache location selector selects locations in a cache for loading new information using either a valid chain, if not all locations already contain valid information, or a history loop otherwise. The valid chain selects the "highest" location in the cache which does not already contain valid information. The history loop selects locations in accordance with a modified form of the First-In-Not-Used-First-Out (FINUFO) replacement scheme. Both the valid chain and the history loop are fully and efficiently implemented in hardware. During normal cache operation, both the valid chain and the history loop continuously seek an appropriate location to be used for the next load. As a result, that location is preselected well before the load is actually required.

Abstract: A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables to obtain therefrom a page table pointer to a selected one of the page tables and then combining a second portion of the logical address and the page table pointer to access the selected page table to obtain therefrom the physical address. If desired, an address space selector may be considered as an extension of the logical address.

Abstract: A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

Abstract: A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot be written into the protect register except during a short, predetermined period after the occurrence of an event such as a reset. The protect register may be written to with information other than the predetermined information at any time. The preferred embodiment comprises a single-chip microcomputer with on-board electrically-erasable programmable read-only memory which is write protected in several, separate blocks.

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), an EPROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and an input pin for providing a RESET signal or programming potential V.sub.PP (23). An EPROM control register (53) in the CPU is loadable under the control of a computer program stored in an external memory (40). Responsive to a first bit in the EPROM control register an address buffer/latch 61 and a data latch 62 temporarily latch address and data information during a write operation to the EPROM. Responsive to a second bit in the EPROM control register the programming potential is applied to the EPROM for a predetermined time to program the data information into the EPROM at its associated address. The accuracy of the programming operation may be verified using the CPU under the control of the external computer program, to compare the address and data information programmed into the EPROM with the original source of such information.

Abstract: A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the transistor of the memory cell, the buried layer is biased to a voltage selected to reduce the maximum voltage across the capacitor. This allows for a reduction in the thickness of the dielectric which coats the trench which increases the capacitance of the capacitor. When the buried layer is of the opposite conductivity type from the transistor type of the memory cell, there is no parasitic MOS transistor formed between the primary portion of the capacitor plate and the source of the transistor of the memory cell.

Abstract: A method for directly providing a conversion of an analog input signal to a digital signal in two's complement code with a sampled data converter. Positive and negative reference voltages and an analog ground voltage are required. After a sign bit determination of the input signal is made, the data converter is coupled between either a first pair of reference voltages or a second pair of reference voltages depending upon the sign bit. The first pair of reference voltages comprises the positive reference and ground reference, and the second pair of reference voltages comprises the ground reference and a negative reference. By selectively coupling the chosen reference voltages to the converter, a converter may directly output two's complement code.

Abstract: A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Abstract: A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row is provided to replace a defective row from the main array. A programmable redundant decoder is programmable to select the redundant row in response to the predecoder signals which select the defective row.

Abstract: A CMOS sense amplifier for use in a memory comprises two CMOS differential amplifiers. Each differential amplifier receives the same two signals generated from a selected bit line pair and each provides a different one of a complementary pair of signals. Each differential amplifier has a current mirror for loads. Each differential amplifier uses a transistor current source. A transistor will operate as a more ideal current source if it is in saturation. The transistor current source is biased by the current mirror of the differential amplifier of which it is a part. The resulting differential amplifier thus has a transistor current source which is biased closer to saturation than if biased by a normal clock signal which is either at the high or low power supply voltage. The self-biasing aspect avoids the problems associated with generating a special reference voltage for the differential amplifier.

Abstract: A CMOS circuit having a differential input stage which provides a single output is provided. An output stage has a capacitor which is used as a Miller integrator coupled thereto for frequency stabilization. A cascode portion is coupled to the Miller integrator to maintain one of the capacitor's electrodes at a predetermined voltage potential. A compensation portion is coupled to the cascode portion to compensate for power supply induced errors created when either an N-channel transistor in an N-well process or a P-channel transistor in a P-well process is used in the cascode portion.

Abstract: A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

Abstract: An analog two pole filter is provided which uses a single amplifier to implement a predetermined transfer function. The filter has a differential input and converts the two inputs to a single output utilizing the same amplifier which performs the filtering function. By coupling a capacitor across the differential input and utilizing the differential aspect of the input signals, the capacitor may be implemented with half the capacitance otherwise required to implement the predetermined transfer function, thereby minimizing circuit area.

Abstract: A data interface circuit for use when interfacing between two communication links communicating frames of digital data in PCM and ADPCM formats is provided. The data interface circuit provides control information for selecting one of a plurality of algorithms to control the transformation of data between a plurality of PCM and ADPCM formats. A single encoded control signal is utilized to establish frame boundaries and to select a predetermined one of the plurality of algorithms to use in converting between PCM and ADPCM data.

Abstract: A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

Abstract: A numeric data processor having an execution unit adapted to efficiently execute the complete set of floating point operations recommended by the IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std. 754-1985, in full compliance therewith. The numeric data processor is also adapted to evaluate a large set of transcendental functions, including trigonometric, logarithmic and exponential, consistent with the IEEE Standard, without requiring a "software envelope." In the processor, special hybrid forms of Volder's CORDIC digital approximator and Meggitt's digital approximator are implemented in a manner so as to require minimal additions or modifications to the form of the execution unit which is otherwise required just to execute the standard floating point operations.

Abstract: Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

Abstract: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.