Abstract: A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Abstract: A capacitor structure including a conductive layer and a dielectric layer is provided. The conductive layer includes a first pattern and a second pattern arranged alternatively with respect to each other. In addition, the dielectric layer is disposed between the first spiral pattern and the second spiral pattern. Since in the capacitor structure described in the present invention, the first pattern and the second pattern being used as electrodes are disposed in a spiral shape, the capacitance per unit area of the capacitor structure is increased.

Abstract: A microcontroller device for extending memory address space by inserting a waiting state and an operation method on the device. The device includes a CPU, a ROM, and a memory interface controller. In the device, the memory interface controller inserts a waiting state into the CPU when address of the information or the program to be fetched by the CPU is not located within a predetermined address range until the information or the program is completely fetched.

Abstract: A liquid crystal display driving circuit, verifying apparatus and error tolerance method is disclosed. The liquid crystal display driving circuit has a plurality of driving stages each having a plurality of verifying apparatus, a logic operation unit and a driving switch. Each verifying apparatus comprises a storage unit, a data switch and an edge detector. The storage unit receives a first and a second trigger pulse during a first and a second time period and then outputs a first and a second shifted signal that correspond to the first and the second triggered pulse submitted to the storage unit. The first and the second shifted signal are transferred to a first and a second output path through switching the data switch during the first and the second time period. The edge detector receives the first shifted signal and set the second output path to a pre-defined logic potential during the second time period if no edge transition is detected during the first time period.

Abstract: An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.

Abstract: A MOS device for an electrostatic discharge protection circuit provided. A gate structure is disposed on the substrate. A source region and a drain region are formed in the substrate beside the gate structure. A doped layer is disposed underneath the source region and the drain region within the substrate but apart from the source region and the drain region. An extended doped region is disposed within the substrate adjacent to the doped layer and the source region. Two parasitic bipolar junction transistors (BJT) are formed in the MOS device. One BJT includes the drain region, the substrate and the source region. Another BJT includes the drain region, the substrate and the doped layer. A discharge current flowing into the drain region is channeled to a common voltage terminal via these two parasitic bipolar junction transistors.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

Abstract: An electrostatic discharge protection device with high voltage and negative voltage tolerance is provided. The electrostatic discharge protection device comprises: a first type substrate; a first type well inside the first type substrate, the first type well being floating; a second type well inside the first type substrate, the second type well separating the first type well from the first type substrate, the second type well being coupled to a first voltage line; a second type first doped region inside the first type well and coupled to a second voltage line; a second type second doped region inside the first type well and coupled to the pad; and an isolation structure between the second type first doped region and the second type second doped region.

Abstract: A pad backer is described, comprising a backing plate, an elastomer layer and a pad backing ring. The elastomer layer has a bottom surface bonded to the backing plate and an upper surface with a protrudent part at the edge portion thereof. The pad backing ring has an inner bottom surface with a recessed part thereon matching with the protrudent part on the upper surface of the elastomer layer, such that the elastomer layer is fixed onto the pad backing ring through engagement of the protrudent part and the recessed part.

Abstract: A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.

Abstract: A chip structure can reduce the phenomenon of overcrowding current at the conventional circular opening of the passivation layer and further causing electromigration when the current flows to the bonding pad via the transmission line. The improved structure for the side profile of the opening of the passivation layer is about a circular profile, but the portion near to the transmission line is a straight line or a curving line. When the current flows through this opening, the current density can be uniformly distributed along the straight line or the curving line, and whereby the phenomenon of overcrowding current can be reduced.

Abstract: A method of state maintenance for a MMC system. The method includes using a plurality of signals, including a working voltage signal, a low voltage detection (LVD) signal, an LVD interrupt signal, a firmware polling signal, an LVD interrupt reset signal. The LVD signal responds to a voltage level of the working voltage at a preset voltage level. The LVD interrupt signal responds to the level of the LVD signal. After the LVD signal returns to the high level state and the firmware polling signal does the polling action to the LVD interrupt signal, then the LVD interrupt reset signal is issued to reset the LVD interrupt signal.

Abstract: A manufacture method of a pixel structure is provided. A gate is formed over a substrate, and a gate insulator layer is formed over the substrate covering the gate. A semiconductor layer is formed over the gate insulator layer and a metal layer is formed over the semiconductor layer. A first mask layer is formed on the metal layer, and the metal layer is patterned to form a source/drain by using the first mask layer as etching mask. Afterward, a second mask layer is formed on the first mask layer and further covers a region between the source/drain. The semiconductor layer is patterned by using the first and second mask layers as etching mask, and then the first and second mask layers are removed. A passivation layer is formed over the substrate. A pixel electrode is formed on the passivation layer. The pixel electrode is electrically connected with the drain.

Abstract: A circuit for generating a reference voltage of an image sensor is provided. The circuit comprises a signal differential amplifier, a gain amplifier, a source follower and a clamp circuit. The signal differential amplifier is adapted for receiving and comparing a bias voltage and the reference voltage, and outputting a first voltage according to a comparison result. The gain amplifier is coupled to the signal differential amplifier, and is adapted for receiving the first voltage and outputting a second voltage. The source follower, coupled to the gain amplifier, and is adapted for receiving the second voltage and outputting the reference voltage. The clamp circuit is coupled to the source follower, and is adapted for receiving the reference voltage and limiting the reference voltage to below a clamp voltage.

Abstract: A charge-pump circuitry which receives an external voltage source to generate a target voltage is provided. The charge-pump circuitry comprises a voltage multiplier module and a voltage difference generating circuitry. Wherein, a first input terminal of the voltage multiplier module receives the external voltage source, and the voltage multiplier module generates a multiplied-voltage according to the external voltage source. The voltage potential of the multiplied-voltage is a predetermined times of the voltage potential of the external voltage source. The voltage difference generating circuitry generates a correcting voltage which is input to a second input terminal of the voltage multiplier module. The voltage potential of the correcting voltage is the potential difference between the target voltage and the multiplied-voltage.

Abstract: A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

Abstract: A button apparatus with a speaker (100) has a frame (104), a speaker (108), a flexible PCB (110), a metal dome (114), a rubber layer (116), and an operating button (120,124). The frame has a cavity (106) and the speaker is securely received in the cavity. The flexible PCB is located on the frame. The metal dome is located on the flexible PCB, and adapted to electrically connect with the flexible PCB. The rubber layer is located on the flexible PCB. The rubber layer has a protrusion (118) to press the metal dome so that the metal dome is electrically coupling to the flexible PCB. The operating button is located on the rubber layer. The button is adapted to press the protrusion, which in turn presses the metal dome.

Abstract: A method for reading an automatically adaptive memory card and a memory card controller are provided. First, whether a present reading address of a reading command is the same as a previous reading address is determined. Next, when the present reading address is determined to be the same as the previous reading address, a response is output and a data is output in a data-lag mode to output the data after the response is outputted. On the other hand, when the present reading address is not the same as the previous reading address, the previous reading address is updated to be the present reading address, the response is output and the data is output in a data-parallel mode to output the data regardless of whether or not the response is outputted. Hence, the memory card with the invention is compatible with several card readers on the market.

Abstract: A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

Abstract: An emergency lighting equipment with an automatic charge/discharge and monitoring system is provided. The emergency lighting equipment comprises an operating mode control circuit, a rectify/voltage-divide and voltage regulation circuit, a main control unit, an illuminating apparatus and a battery. A battery discharge operating is initiated when the main control unit detects the passage of a preset period without any battery discharge operation. The main control unit also terminates a battery discharging operation when the discharge operation is completed and terminates a battery charging operation after the battery has been float-charged for a preset period of time. The emergency lighting equipment may include a battery state inspection circuit for issuing a warning signal when the battery is found to be defective.