Abstract: A structure is to affix an optical plate on a frame in a panel display. The optical plate has a protruding region with a slit. The structure includes a first hook-like member, disposed on one side of the frame and having an extending portion for passing through the slit and hooking the protruding region of the optical plate. A blocking member is disposed on the side of the frame and separated from the first hook-like member, having a sidewall against an edge of the protruding region of the optical plate.

Abstract: A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are sequentially disposed on the substrate. The first control gate and the second control gate are respectively disposed on the sidewalls of the silicon stripe, while the source/drain regions are configured in the silicon stripe beside both sides of the first control gate and the second control gate. The composite dielectric layers are disposed between the first control gate and the silicon stripe, and between the second control gate and the silicon stripe. Since a single memory structure can store a multiple bit of information, it is advantageous for minimizing devices.

Abstract: A method of fabricating a pixel structure of TFT LCD is provided. First, a gate pattern, pixel electrode pattern, gate isolating layer and semiconductor layer are formed over the substrate sequentially. Then, a patterning process is performed to remove the first metal layer over the pixel electrode pattern, wherein the gate isolating layer and semiconductor layer are retained over the gate pattern. Next, a source pattern and drain pattern are sequentially formed over the substrate, and then a passivation layer and photoresist layer are formed over the substrate. Thereafter, a back side exposure process and a patterning process are performed by using the gate pattern, source pattern and drain pattern as mask to pattern the photoresist layer. Thereafter, the passivation layer is etched by using the patterned photoresist layer as mask to expose the transparent conductive layer of the pixel electrode pattern. Finally, the photoresist layer is removed.

Abstract: A method for the preparing pure, thermally stable and high surface area ceria is described, wherein the ceria maintains a surface area of 12 m2/g after calcination at 980° C. in air for 4 hours. In the method, an aqueous solution containing Ce3+, Mg2+, organic acid and organic polymer is prepared and then evaporated to obtain a gel. The gel is calcined to obtain a mixed oxide, and then MgO is leached from the mixed oxide with a solvent to obtain raw ceria. The raw ceria is then washed, filtered and dried to obtain a ceria product.

Abstract: The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

Abstract: An A/D converter with adjustable internal connection and a method for operating the same are provided. The A/D converter comprises: a plurality of piezo-transforming devices for detecting an input voltage from the alternating current source and adjusting an connection of input terminals of the plurality of piezo-transforming devices based on the input voltage to obtain an input/output voltage ratio of the plurality of piezo-transforming devices inversely proportional to the input voltage.

Abstract: A non-volatile memory device and method of manufacturing the same is provided. A substrate is provided and then a trench is formed in the substrate. Thereafter, a bottom oxide layer, a charge-trapping layer and a top oxide layer are sequentially formed over the substrate and the surface of the trench. A conductive layer is formed over the top oxide layer filling the trench. The conductive layer is patterned to form a gate over the trench. The top oxide layer, the charge-trapping layer and the bottom oxide layer outside the gate are removed. A source/drain doping process is carried out. Because the non-volatile memory device is manufactured within the trench, storage efficiency of the device is improved through an increase in the coupling ratio. Furthermore, more charges can be stored by increasing the depth of the trench.

Abstract: An apparatus for measuring the optoelectric properties of an organic light-emitting device (OLED) comprising a platform, a goniometer, a three-axis moving device and a computer. The goniometer is disposed on one side of the platform and an OLED is disposed on the goniometer. The three-axis moving device is disposed on another side of the platform. The photo-detector is disposed on the three-axis moving device with the photo-detector toward the OLED on the goniometer. The goniometer, the three-axis moving device and the photo-detector are connected to the computer.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: A detection and repair system includes an optical microscope, an image-retrieving device, an emission detector, a data controller, and a laser beam generator. When detecting the location of a defect, the system charges a detected region of an organic electroluminescent device with a negative bias or low forward bias before the device is lighted on. Then, the emission detector detects the locations of defects, which generate emission such as photons, thermal or IR emission, in an enlarged image. The laser beam generator generates a laser beam, which is used to isolate one of the defects. Furthermore, this invention also discloses a method for detecting and repairing an organic electroluminescent device.

Abstract: An integrated driver device frame of a liquid crystal display panel is provided. The integrated driver device frame comprises a plurality of driver units, a plurality of driver lines and a plurality of output terminals. Each output terminal is coupled to a corresponding pixel element respectively. In the integrated driver device frame of the invention, the plurality of driver units is arranged with two staggered rows, in order that the driver unit width is larger than the interval of every neighboring two output terminals and is less than two times of the interval. Accordingly, the interval of two neighboring output terminals can be equal to the pixel pitch and the dot-per-inch resolution of the LCD panel can be enhanced.

Abstract: A power supply apparatus and a power supply method are described, wherein the non-polar characteristics of the electrodes of a capacitor is utilized to improve the energy utilization efficiency of a battery through reciprocating switches of polarity connection between the battery and the capacitor. The voltages of the capacitors can also stay at a near constant level using the polarity reversal mechanism.

Abstract: A method of fabricating a pixel structure is provided. A gate, an insulation layer, and a channel layer are sequentially formed over the substrate. A pair of source/drain terminals are formed over the channel layer, consisting a thin film transistor on the substrate. A passivation layer is formed over the thin film transistor. A photoresist layer is formed over the passivation layer. Using the gate, the source/drain terminals as a mask, a back exposure and a photoresist development process are performed to pattern the photoresist layer. Using the patterned photoresist layer as a mask, the passivation layer and the insulation layer are etched to expose a sidewall of the drain terminal. The photoresist layer is removed. A pixel electrode is formed over the passivation layer such that the pixel electrode and the drain terminal are electrically connected through the sidewall of the drain terminal.

Abstract: A thin-film transistor array substrate, used in a transflective liquid crystal display. The thin-film transistor array substrate has a substrate, a plurality of pixels, a plurality of scan lines and a plurality of data lines. Each of the pixels has a transparent sub-pixel and a reflective sub-pixel, while the transparent sub-pixel further has a transparent electrode and a first thin-film transistor, and the reflective sub-pixel has a reflective pixel electrode and a second thin-film transistor. The pixel electrode of each sub-pixel is thus electrically connected to a different thin-film transistor. The step of forming a molybdenum layer is thus not required, saving fabrication cost.

Abstract: A method for fabricating a trench power MOSFET, comprising an epitaxial layer and a mask layer formed over a substrate, a trench formed in the epitaxial layer and the mask layer, a gate oxide layer formed on the trench, then the mask layer removed, a body well region formed in the epitaxial layer beside the trench, a source region formed in and adjacent to the body well region, and a spacer formed on the sidewalls of the exposed gate layer exposing the source region partially. Masking by spacer, an opening exposing the body well is formed by partially removing the source region and the gate layer. A body region is formed in the body well region under the opening. A silicide layer is formed on the surfaces of the gate layer and the opening.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.

Abstract: For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.

Abstract: A zooming lens is suitable for projecting images produced by a display device onto a screen. The zooming lens includes a first set of lenses and a second set of lenses, wherein the second set of lenses is disposed in the optical path between the first set of lenses and the display device. The first set of lenses includes first lens, second lens, third lens, and fourth lens sequentially, and the fourth lens is adjacent to the second set of lenses. The second set of lenses includes fifth lens, sixth lens, seventh lens, and composite lens sequentially, and the composite lens is adjacent to a side of the display device. The optical focusing of the lenses, from the first one through the seventh and to the composite lens, are positive, negative, negative, positive, positive, negative, positive value and positive, respectively. The composite lens includes two optical lenses.

Abstract: A two phase internal voltage generator at least includes a first phase internal voltage generator and a second phase internal voltage generator. The power consumption of the second phase internal voltage generator is relatively lower than that of the first phase internal voltage generator. The first phase internal voltage generator promptly generates and provides a first internal voltage source when an external power is provided. As a second internal voltage source that is provided by the second phase internal voltage generator is stable, the first phase internal voltage generator cuts off the supply of the first internal voltage source. The present invention prevents the problem to major power consumption for conventional internal voltage generator.

Abstract: A pipeline accessing method to a large block memory is described. The large block flash memory has a plurality of pages and each page has a plurality of sectors. The memory device has a controller to control an access operation between a host and a cell array of the large block flash memory with a page buffer. The controller includes at least two buffers, when the host intends to program the memory device. In the method, data sectors are transferred between the host and the large block flash memory by alternatively using the buffers. After transferring N data sectors with respect to one page, a start program command is issued by the controller for programming the data.