Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: An organic light-emitting display is provided. The organic light-emitting display has a power line divided into multiple sets with a voltage terminal attached to the center of each power line set. Furthermore, all the voltage terminals are coupled to a power supply through a low resistance conductive material medium. With this setup, brightness imbalance between neighboring pixels is minimized.

Abstract: An integrated transformer with a stack structure comprises a middle dielectric layer, a bottom dielectric layer, a first winding and a second winding. A portion of the first winding is disposed over a surface of the middle dielectric layer and the remaining portion of the first winding is disposed over a surface of the bottom dielectric layer. A portion of the second winding is disposed over the surface of the middle dielectric layer and the remaining portion of the second winding is disposed over the surface of the bottom dielectric layer. The second winding doesn't intersect with the first winding. The portions of the first and second windings over the surface of the middle dielectric layer connect with the remaining portions of the first and second windings over the surface of the bottom dielectric through via plugs.

Abstract: A cassette for holding substrate in a load-lock comprising an outer casing having a front surface with multiple slots and two sidewalls having holes at the bottom section thereof. Braces are set at the corner edges inside the outer casing and side plates are attached to the braces. Each slot has a set of side plates attached to the braces for holding a substrate. Obstruction pieces are also set inside the outer casing near the corresponding holes. Each obstruction pieces comprise a fixed part and an obstructing part. The fixed part attaches firmly to a bottom plate of the outer casing, and the obstructing part blocks the corresponding hole on the outer casing.

Abstract: An antenna calibration system consists mainly of a signal source, an antenna, a first radio frequency mixer, a first local oscillator, an power detecting device, a personal computer, and a servo amplifier. The signal source emits a signal, and the antenna receives the signal. The signal and the first local oscillator, which emits a signal, are emitted into the first radio frequency mixer. Then the first radio frequency mixer emits a signal into the energy detecting device which calculates the signal power, and transmits the power into the personal computer. The personal computer calculates the powers, and then transmits an angle control signal into the servo amplifier. The servo amplifier amplifies the signal, and then drives the antenna pedestal to turn until the antenna is aimed at the signal source. This can calibrate exactly the antenna's azimuth and elevation offset angle.

Abstract: An electrical product and a tilting control device thereof are provided. The tilting control device comprises a shell body, a light source, at least a transparent box, an opaque element, a plurality of photo-sensing units and a logic circuit. The light source is disposed inside the shell body for emitting light. The transparent box is disposed along the path of the light inside the shell body. The opaque element is supported by a carrier surface within the transparent box. The photo-sensing units are disposed inside the shell body at each end under the transparent box. When the tilting control device tilts, the opaque element will move towards one end of the transparent box so that a portion of the light traveling to the photo-sensing unit is obstructed. The logic circuit is coupled to the photo-sensing units for outputting a signal according to the light intensity detected by the photo-sensing units.

Abstract: A method for manufacturing a non-volatile memory. The method comprises steps of forming a first dielectric layer on a substrate and forming a dummy gate layer on the first dielectric layer. Further, the dummy gate layer is defined to form a plurality of dummy gates and a doped region is formed in the substrate by using the dummy gates as a mask. A second dielectric layer is formed on a portion of the first dielectric layer corresponding to the location of the doped region and the dummy gates are removed to expose a portion of the first dielectric layer. A conductive layer is formed over the substrate to cover the second dielectric layer and the first dielectric layer.

Abstract: A driving method is used for driving the voltage-driven circuit of an organic light emitting diode display device. Within a frame period, data voltage is set to a negative data voltage for a pre-defined interval within a frame period. When the scanning voltage is set to a high voltage level, the negative data voltage is applied to the gate terminal of a driving thin film transistor. The gate remains at the negative gate voltage for a maintenance period and the driving thin film transistor has a constant threshold voltage. Hence, this invention provides a mechanism for maintaining a constant luminance from the organic light emitting diode despite an extended use, thus effectively increasing the working life of the display device.

Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

Abstract: An optical lens molding apparatus includes a cylindrical mold, a first mold core, a second mold core and a correctional ring. The first and the second mold core have a columnar shape and are disposed inside the cylindrical mold to form a cavity. Furthermore, the first and the second mold core have a planar portion at the end surface facing the cavity. The correctional ring is disposed on the planar portion of the second mold core. The correction ring corrects any face tilting of the molded optical lens due to the tilting of the first mold core. The present invention also provides a precision molding apparatus for forming precision parts.

Abstract: A Viterbi decoder of a partial response maximum likelihood channel. In an optical disc drive, a system of partial response maximum likelihood has an analog/digital converter. This analog/digital converter receives an analog signal and outputs a digital signal to a Viterbi decoder. The Viterbi decoder has an adaptive level Viterbi decoder, a signal level mapping algorithm, a received signal delay chain, a hard decoder, and a multiplexer. The adaptive level Viterbi decoder and the hard decoder receive a digital signal output from the analog/digital converter to decode simultaneously. Whether the output of the multiplexer is the decision bit of the adaptive level Viterbi decoder or the hard decoder is determined by the mode selection algorithm.

Abstract: A handwriting recognition device using fuzzy logic and cellular neural network for unconstrained handwritten numeral classification is provided. The current mode VLSI classifier has a I/O circuit for inputting and outputting a plurality of membership functions. An extraction unit comprising a CCD extractor with a CNN structure and a compression unit receives a to-be-recognized character having a plurality of input features for generating a plurality of features values after compression. A membership function generator stores the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type membership degrees. A plurality of switched-current integrators receives the plurality of current-type membership degrees for generating a plurality of synthesis membership degrees.

Abstract: An FPD encapsulation apparatus at least comprises a chamber and a pressing mechanism. In this case, the chamber has an airtight space to provide a low-pressure environment, and the low-pressure environment is located inside the airtight space. The pressing mechanism is disposed within the chamber, and the pressing mechanism is operated in the low-pressure environment for pressing a second substrate to bind a first substrate and the second substrate. Furthermore, a method for encapsulating an FPD is disclosed. The method comprises providing a first substrate, forming an adhesive on the first substrate, providing a second substrate to align the first substrate and face to the adhesive, providing a low-pressure environment for the first and second substrates, and binding the first and second substrates to form the FPD.

Abstract: An redundant array of independent disks (RAID) storage device is provided. The RAID comprises M number of storage devices, and the storage blocks of the same J-column in each storage device comprises complete stripe blocks and at least a plurality of partially complete stripe blocks. Inside the same stripe block, the total number of the storage blocks (L) is smaller than the number of the storage device (M), and the quantity of the storage blocks (M) is not multiple of storage blocks (L).

Abstract: A polishing pad having a polishing surface, a back surface and a sidewall is provided. The sidewall is connected to the polishing surface and the back surface. The polishing pad includes a polishing region and a region neighboring to the polishing region. Wherein, at least one stress buffer pattern is designed in the neighboring region. The stress buffer pattern is formed to buffer the stress created during a polishing process to prevent the region from being protruded and thus prevent the surface of the region, once protruded, from rubbing against the wafer carrier to generate particles, so that contamination of the surface of the wafers can be avoided. On the other hand, at least one cambered surface can be designed on the sidewall of the polishing pad to prevent the sidewall from rubbing against the wafer carrier to generate particles, so that contamination can be avoided.

Abstract: A circuit to characterize the matching of energy-storage components is provided. The circuit includes a linear resistor and a power source. The circuit is electrically connected to two serially connected energy-storage elements, for example, a pair of capacitors. The matching between the two capacitors can be evaluated by measuring the slopes of a function relating the input and the output voltageof the circuit.

Abstract: A manufacturing method for a keypad is provided. First, a patterned thin plastic sheet, which includes a first surface and a second surface, is provided. A plurality of touch buttons which can be operated independently are included. The touch buttons have a plurality of hollow patterned structures on them. Later, a metal layer is formed on the first surface of the patterned thin plastic sheet and on the sidewalls of the hollow patterned structures. Thereafter, an adhesion enhancing layer is added onto to the second surface of the patterned thin plastic sheet. Later, a colored layer is formed on the adhesion enhancing layer. Finally, a protruding point layer is formed on the adhesion enhancing layer, and is covering the colored layer. The protruding point layer has a plurality of protruding points with positions corresponding to the touch buttons respectively.

Abstract: A thin film transistor array including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes is provided. The scan lines and the data lines are disposed over the substrate to define a plurality of pixel areas. Each thin film transistor is disposed in one of the pixel areas and driven by the corresponding scan line and data line. The etch barrier layer including a plurality openings is disposed over the scan line or a common line. Each pixel electrode electrically connected to the corresponding thin film transistor is disposed in one of the pixel areas, wherein a portion of each pixel electrode is coupled to the corresponding scan line through one of the openings to form a storage capacitor. Furthermore, a fabricating method of the thin film array is also provided.

Abstract: A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.

Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate in the trench. A heating process is performed to form a source/drain area in the substrate under the doped metal silicide layer. Thereafter, a first conductive layer is formed on the doped metal silicide layer to fill up the trench.