Patents Represented by Attorney Joan Pennington
  • Patent number: 8352707
    Abstract: A method and a storage system are provided for implementing host logical address to physical memory address mapping for persistent storage media including flash memory. Numerical compositions at multiple levels of granularity are used to store the logical address to physical memory address mappings. A plurality of groupings, each grouping including a fixed number of blocks is encoded using recursive composition, eliminating the need to store separate lengths.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: January 8, 2013
    Assignee: HGST Netherlands B.V.
    Inventor: David Robison Hall
  • Patent number: 8352902
    Abstract: A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas Charles Brennan, Robert Francis Lembach
  • Patent number: 8343804
    Abstract: A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Kyu-hyoun Kim
  • Patent number: 8340163
    Abstract: A method and dual watchdog communication circuit for implementing single line asynchronous dual watchdog communication for electrostatic discharge (ESD) immunity, and a design structure on which the subject circuit resides are provided. The dual watchdog communication circuit includes a source transceiver module and a sink transceiver module connected together by a single line, each of the source transceiver module and the sink transceiver module uses a coded pulse for the single line asynchronous dual watchdog communication.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventor: Don A. Gilliland
  • Patent number: 8340112
    Abstract: A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Phillip Rogers Hillier, III, David Alan Shedivy, Kenneth Michael Valk
  • Patent number: 8324933
    Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joel T. Ficke, David M. Friend, Grant P. Kesselring, James D. Strom, Jianguo Yao
  • Patent number: 8314386
    Abstract: An X-ray spectrometer systems and methods are provided for implementing signal detection for use on electron-optical beam lines and microscopes. The X-ray Spectrometer System (XSS) includes an X-ray detector (XD) measuring the X-ray signal and positioned proximate to a specimen. An environmental isolation window together with an electron beam stop is disposed between XD and the specimen. The environmental isolation window and the electron beam stop protect XD from electrons directly transmitted through the specimen. An electron detector is located between the electron beam stop and the specimen allowing the measurement of scattered electrons. The XD measures an X-ray signal in the X-ray spectrometer system.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 20, 2012
    Assignee: UChicago Argonne, LLC
    Inventor: Nestor J. Zaluzec
  • Patent number: 8316333
    Abstract: A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Darsow, Timothy D. Helvey
  • Patent number: 8300450
    Abstract: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, John Edwards Sheets, II
  • Patent number: 8296707
    Abstract: A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael David Amundson, Craig Marshall Darsow, Eldon Gale Nelson, Dennis Martin Rickert
  • Patent number: 8275908
    Abstract: A method and apparatus are provided for implementing service requests from a common database in a multiple dynamic host configuration protocol (DHCP) server environment. A DHCP authorization cache is provided to implement synchronized access for the multiple DHCP servers to the common database. The DHCP authorization cache includes a plurality of elements, each element for storing a plurality of entries including a client identifier, an ISCSI DHCP router pointer, an ISCSI DHCP router pointer alternate, and a timestamp and the DHCP authorization cache includes an entry pointer initially set to zero.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Josep Cors, Chung Meng
  • Patent number: 8275922
    Abstract: A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wayne Melvin Barrett, Kenneth Michael Valk
  • Patent number: 8271801
    Abstract: A method, apparatus and a data storage device are provided for implementing data confidentiality and integrity of data stored in overlapping, shingled data tracks on a recordable surface of a storage device. A unique write counter is stored for each zone written to the recordable surface of the storage device. An encryption key is used together with the write counter information and a logical block address to encrypt each sector being written, and to decrypt all sectors being read. An individual sector is decrypted, obtaining the write counter information and reading the data sector. A message authentication code is stored for each zone. All sectors of the zone are read to perform integrity check on a sector.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 18, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Cyril Guyot
  • Patent number: 8271923
    Abstract: A method, system and computer program product are provided for implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip. A common path pessimism removal algorithm is enhanced by a forward tracing parallel clock tree proximity credit algorithm that uses forward tracing, and computes a proximity credit that is applied to reduce pessimism in the static timing.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Darsow, Timothy D. Helvey
  • Patent number: 8251749
    Abstract: A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: August 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Richard Dangler, Matthew Stephen Doyle, Thomas Donald Kidd, Joseph Kuczynski, Kevin Albert Splittstoesser, Timothy Jerome Tofil
  • Patent number: 8250380
    Abstract: A method and apparatus are provided for implementing secure erase for solid state drives (SSDs). An encryption key is used to encrypt data being written to SSD. A controller identifies a key storage option, and responsive to the identified key storage option, stores a key for data encryption and decryption. The controller deletes the key within the SSD responsive to the identified key storage option, ensuring that once the key is deleted, the key is not recoverable and data is effectively erased.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: August 21, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Cyril Guyot, Zvonimir Z. Bandic, Yuval Cassuto, Adam Michael Espeseth, Marco Sanvido
  • Patent number: 8237510
    Abstract: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joel T. Ficke, Grant P. Kesselring, James D. Strom
  • Patent number: 8228913
    Abstract: A method and apparatus are provided for implementing system to system communication in a switchless non-InfiniBand (IB) compliant environment. IB architected multicast facilities are used to communicate between HCAs in a loop or string topology. Multiple HCAs in the network subscribe to a predetermined multicast address. Multicast messages sent by one HCA destined to the pre-determined multicast address are received by other HCAs in the network. Intermediate TCA hardware, per IB architected multicast support, forward the multicast messages on via hardware facilities, which do not require invocation of software facilities thereby providing performance efficiencies. The messages flow until picked up by an HCA on the network. Architected higher level IB connections, such as IB supported Reliable Connections (RCs) are established using the multicast message flow, eliminating the need for an IB Subnet Manager (SM).
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy Roy Block, Thomas Rembert Sand, Timothy Jerry Schimke
  • Patent number: 8223921
    Abstract: Sensing methods and a compact, sample holding pin base sensor are provided for detecting if a sample pin is, for example, properly mounted on a goniometer used for automated, high throughput macromolecular crystallography. A first magnet is used for holding a magnetic base; a second magnet is disposed spaced apart from the first magnet. The first magnet and the second magnet have opposite orientation. A Hall-effect switch is located generally centrally between the first magnet and the second magnet. A state of the Hall-effect switch indicates if a sample pin is properly mounted on a mounting member, such as a goniometer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 17, 2012
    Assignee: UChicagoArgonne, LLC
    Inventors: Oleg Makarov, Shenglan Xu, Robert F. Fischetti
  • Patent number: 8213249
    Abstract: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer