Patents Represented by Attorney Joan Pennington
  • Patent number: 7774357
    Abstract: A method, apparatus and computer program product are provided for implementing enhanced query governor functions. Query execution includes first checking for a timeout value for a query. Responsive to identifying a timeout value for the query, an execution time for the query is reset and a monitor for each timeout value for the query is started. Then the execution of the query is started. The execution of predefined events is monitored during the execution of the query. The predefined events include a begin or end of processing of at least one of a trigger and a user defined function (UDF). Execution status of the query is periodically checked. Responsive to identifying the query is executing, checking for any expired timeout value is performed. The execution of the query is halted responsive to an identified expired timeout value.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventor: John Matthew Santosuosso
  • Patent number: 7768130
    Abstract: A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Tonti, Chih-Chao Yang
  • Patent number: 7768851
    Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson
  • Patent number: 7769201
    Abstract: A method, apparatus, and computer program product provides automated analysis of thermal imaging data for multi-layer materials based upon a theoretical model of a multi-layer material system, which is solved numerically. The computer-implemented method effectively processes the volume heating effect for thermal barrier coatings (TBCs), since quantitative evaluation of TBC thickness and conductivity is particularly important. TBC thickness is a processing parameter and required to be monitored. TBC conductivity is a measure of TBC quality because it is directly related with TBC density/porosity, microcracking and interface cracks. Because this method is an imaging technology, it can be used for fast and 100% area inspection of larger TBC surfaces, such as combustor liners.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: August 3, 2010
    Assignee: UChicago Argonne, LLC
    Inventor: Jiangang Sun
  • Patent number: 7766172
    Abstract: A method and apparatus are provided for separating elastomeric materials from mixed material streams. A separator includes a bank of parallel rollers extending longitudinally between a first end and a second end. The bank of parallel rollers having a predefined inclination with the first end elevated higher than the second end. Mixed material streams are fed onto a top surface of the high end of the inclined parallel rollers. A material having less friction and elasticity slides down the inclined roller bank top surface are collected into a collection bin positioned adjacent the second, lower end of the roller bank. Other materials having a higher friction coefficient grip the rollers more and are lifted out of the valley due to friction migrating perpendicular to the rotating rollers and are collected in a collection bin positioned adjacent one side of the roller bank parallel to the longitudinal roller axis.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: August 3, 2010
    Assignee: UChicago Argonne, LLC
    Inventors: Jeffrey S. Spangenberger, Edward J. Daniels, Bassam J. Jody, Joseph A. Pomykala, Jr.
  • Patent number: 7764531
    Abstract: A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, Toshiaki Kirihata, Phil Christopher Felice Paone, Brian Joy Reed, John Matthew Safran, David Edward Schmitt, Gregory John Uhlmann
  • Patent number: 7761658
    Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Larry J. Cravens, Jay Paul Kurtz, Kenneth Gerald Linn, Glen W. Nelson, Kenneth Charles Vossen, Donald L. Ward
  • Patent number: 7760054
    Abstract: An RF cavity is provided with a plurality of tubes that are formed into a tubular cage in a predefined shape to define the RF cavity. A selected number of tubes and a selected tube diameter are provided to form a confinement cage for the RF fields within the RF cavity defined by the tubes. The multiple, small metal tubes are selectively bent to form different cavity shapes and sizes as needed to accelerate the particles and function as a confinement cage for the RF fields within the RF cavity defined by the tubes. The cost to fabricate RF cavities using the tubular cage design is significantly lower than the cost of producing a solid cavity using conventional fabrication technology.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: July 20, 2010
    Assignee: UChicago Argonne, LLC
    Inventors: John W. Lewellen, John Noonan, Terry L. Smith, Geoff Waldschmidt
  • Patent number: 7757006
    Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
  • Patent number: 7752170
    Abstract: Methods, apparatus and computer program product implement enhanced dynamic copy-on-write storage compression. For a write operation, a freed block is detected by the COW storage for compressing freed blocks from the COW storage. Responsive to the detected freed block being a previously written block in the COW storage, the previously written block in the COW storage is deleted from the COW storage. Responsive to the detected freed block not being a previously written block in the COW storage, the block is marked as zero in the COW storage.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventor: David Charles Boutcher
  • Patent number: 7737757
    Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7739241
    Abstract: Methods, apparatus and computer program product implement enhanced dynamic copy-on-write storage compression. For a write operation, a purge function for a block being written is detected by the COW storage for compressing freed blocks from the COW storage. Responsive to the detected purge function and the block being a previously written block in the COW storage, the previously written block in the COW storage is deleted from the COW storage. Responsive to the detected purge function and the block not being a previously written block in the COW storage, the block is marked as zero in the COW storage.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventor: David Charles Boutcher
  • Patent number: 7733722
    Abstract: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
  • Patent number: 7733984
    Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, John Francis Bulzacchelli, Daniel Mark Dreps
  • Patent number: 7729188
    Abstract: A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, Phil Christopher Felice Paone, Brian Joy Reed, David Edward Schmitt, Gregory John Uhlmann
  • Patent number: 7724586
    Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Daniel Mark Nelson
  • Patent number: 7724585
    Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7724022
    Abstract: A method and eFuse circuit for implementing enhanced security features using eFuses, such as disabling selected predefined test, debug, and mission security functions used in application-specific integrated circuits (ASICs), and a design structure on which the subject circuit resides are provided. The eFuse circuit includes a plurality of eFuses, a sense amplifier coupled to the plurality of eFuses, and a plurality of sense output latches coupled to the sense amplifier. The plurality of sense output latches is arranged to have a bias to power up to a known value. Control logic coupled to the plurality of sense output latches provides at least one predefined control signal responsive to the known value of the plurality of sense output latches, which enables a selected predefined security function. The plurality of eFuses is sensed and the ASIC is configured to a predefined state responsive to an applied POR/Sense control signal.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian P. Deskin, William E. Hall, David W. Pruden
  • Patent number: 7725762
    Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis
  • Patent number: 7723816
    Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II