Patents Represented by Attorney Joan Pennington
  • Patent number: 8195589
    Abstract: A method and apparatus are provided for dynamically determining a primary adapter in a heterogeneous N-way adapter configuration. Each of the adapters generates information about itself and exchanges the information with all other adapters. First a decision-making adapter is identified. Then the decision-making adapter compares the adapter-generated information of all the adapters and makes a decision determining the primary adapter. The decision-making adapter communicates the decision to all other adapters. The determined primary adapter assumes a role as the primary adapter and the other adapters assume a role as a secondary adapter.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian Eric Bakke, Robert Edward Galbraith, Brian James King, Timothy James Larson, William Joseph Maitland, Jr., Timothy Jerry Schimke
  • Patent number: 8185662
    Abstract: A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kenneth Michael Valk
  • Patent number: 8170024
    Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kerry Christopher Imming, John David Irish, Joseph Franklin Logan, Tolga Ozguner, Michael Steven Siegel
  • Patent number: 8166357
    Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Warren Pruden, Dennis Martin Rickert, Brian Andrew Schuelke
  • Patent number: 8156501
    Abstract: A method, apparatus and computer program product implement dynamic authority for a user to perform tasks on a resource. A user selected task on a resource is identified and analyzed to determine whether the task changes a state of the resource. When determined that the task changes a state of the resource, then a relationship of the resource to related resources is analyzed. Access to tasks on the resource is dynamically determined for the user based upon the identified relationship of the resource to related resources. Based on the analysis performed, access is denied or a summary of side effects with confirmation is presented.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael John Branson, Gregory Richard Hintermeister, Michael D. Rahn
  • Patent number: 8140833
    Abstract: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Powers Bradford, Richard James Eickemeyer, Timothy Hume Heil, Harold F. Kossman, Timothy John Mullins
  • Patent number: 8135934
    Abstract: A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition. Initially a minimum entitlement of I/O entitled memory capacity is allocated to each of the respective multiple I/O adapters. The minimum entitlement enables operation of an I/O adapter driver. Additional entitlement of I/O entitled memory capacity is selectively allocated based upon I/O demands of each I/O adapter.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Colin R. DeVilbiss, Wayne G. Holm, David B. Murray, Kristopher C. Whitney
  • Patent number: 8130902
    Abstract: Active optics apparatus and method for aligning active optics are provided for a high-resolution, active optic fluorescence analyzer combining a large acceptance solid angle with wide energy tunability. A plurality of rows of correctors selectively controlled to bend an elongated strip of single crystal material like Si (400) into substantially any precisely defined shape. A pair of pushers engages opposite ends of the silicon crystal strip exert only a force along the long axis of the crystal strip, and does not induce additional bending moments which would result in a torsion of the crystal.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: March 6, 2012
    Assignee: UChicago Argonne, LLC
    Inventors: Bernhard W. Adams, Klaus Attenkofer, Oliver A. Schmidt
  • Patent number: 8127083
    Abstract: A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When the received data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated and inverted. The first squash signal and the inverted reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Kundinger, Nicholas D. Lindberg, Eric J. Stec
  • Patent number: 8106360
    Abstract: An infrared (IR) emission spectroscopy and microscopy apparatus with X-ray excitation or electron excitation and an improved process for extending spatial relation of infrared (IR) microscopy and performing microscopic infrared (IR) analysis by X-ray or electron radiation are provided. By utilizing nanometer sized X-ray beams or electron beams to produce IR emission, the spatial resolution of IR microscopy is extended. Simultaneously performing X-ray or electron-based spectroscopy as well as structural studies are enabled.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: January 31, 2012
    Assignee: UChicago Argonne, LLC
    Inventor: Richard A. Rosenberg
  • Patent number: 8103930
    Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wayne Melvin Barrett, Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
  • Patent number: 8103900
    Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Richard E. Fry, Marc A. Gollub, Eric E. Retter, Kenneth L. Wright
  • Patent number: 8098729
    Abstract: A method and apparatus are provided for implementing B-picture scene changes. A prediction stage predicts a B-picture scene change based upon a sequence of statistical information in an encoder order and a reaction stage is responsive to the prediction stage for modifying a quantization scale of a rate control algorithm.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles Edward Boice, Charles John Stein, Krishna Chaitanya Ratakonda, Edward Francis Westermann
  • Patent number: 8089199
    Abstract: Enhanced mechanical designs are provided for weak-link rotary mechanisms for implementing angular rotations with a defined angular travel range and positioning resolution, for example, with ten-degree-level travel range and ten-nanoradian-level positioning resolution. A weak-link rotary structure has a predetermined pattern for implementing angular rotations with repeatable and reliable angular travel range and positioning resolution including a plurality of connecting links radially extending from a central portion with a predefined angular separation between the connecting links; each said connecting link having at least one pair of weak-link connections; alternate connecting links being coupled to a respective terminal, each said respective terminal being mounted to a connecting carriage; remaining other connecting links being coupled to a respective mounting portion of a mating part of the weak-link rotary structure.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 3, 2012
    Assignee: UChicago Argonne, LLC
    Inventors: Deming Shu, Jorg M. Maser
  • Patent number: 8089285
    Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, David W. Kruger, James S. Mason, Richard W. Oldrey
  • Patent number: 8085550
    Abstract: A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff structure having a selected geometry is defined on the base SMT pad to increase thickness of the solder joint for the connector.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark Kenneth Hoffmeyer, Steven Paul Ostrander, Sri M. Sri-Jayantha
  • Patent number: 8083067
    Abstract: Enhanced methods for separating of overlapping density porous materials are provided. The methods of the invention exploit the differences in the porosity of porous feed materials compared to that of the solid plastics. In the first stage, air is forced out of the pores of a porous feed material. In the second stage, a solution, having the appropriate density, is forced into the pores. This increases the density of the porous material relative to the density of the solid plastics. As a result, the porous material can be made to sink, while the solid plastics continue to float.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: December 27, 2011
    Assignee: UChicago Argonne, LLC
    Inventors: Joseph A. Pomykala, Jr., Bassam J. Jody, Edward J. Daniels, Jeffrey S. Spangenberger, Scott T. Lockwood
  • Patent number: 8086924
    Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
  • Patent number: 8065575
    Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: November 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
  • Patent number: 8056018
    Abstract: Conflict resolution of web application keyboard shortcuts implementation includes a web application being loaded in a web browser and application keyboard shortcuts for the web application are registered with the web browser. The web browser identifies application keyboard shortcuts for the web application that conflict with keyboard shortcuts for the web browser. Then the web browser resolves each conflict.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anthony Wayne Erwin, Timothy Charles Mossing, Christopher A. Robbins, Brian Owen Wood