Abstract: A method and apparatus are provided for dynamically determining a primary adapter in a heterogeneous N-way adapter configuration. Each of the adapters generates information about itself and exchanges the information with all other adapters. First a decision-making adapter is identified. Then the decision-making adapter compares the adapter-generated information of all the adapters and makes a decision determining the primary adapter. The decision-making adapter communicates the decision to all other adapters. The determined primary adapter assumes a role as the primary adapter and the other adapters assume a role as a secondary adapter.

Abstract: A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.

Abstract: A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintained for tracking a current position for frame alteration operations in the packet. The stake is maintained for tracking a start of a current header for frame alteration operations in the packet. The current pointer is used by frame alteration code instructions to specify a sequence of operations relative to the current pointer. The specified frame alteration sequence is compact in terms of code size to operate on data within a small window of bytes. Advance pointer instructions allow the current and stake pointers to be advanced an arbitrary number of bytes into the packet.

Abstract: A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.

Abstract: A method, apparatus and computer program product implement dynamic authority for a user to perform tasks on a resource. A user selected task on a resource is identified and analyzed to determine whether the task changes a state of the resource. When determined that the task changes a state of the resource, then a relationship of the resource to related resources is analyzed. Access to tasks on the resource is dynamically determined for the user based upon the identified relationship of the resource to related resources. Based on the analysis performed, access is denied or a summary of side effects with confirmation is presented.

Abstract: A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.

Abstract: A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition. Initially a minimum entitlement of I/O entitled memory capacity is allocated to each of the respective multiple I/O adapters. The minimum entitlement enables operation of an I/O adapter driver. Additional entitlement of I/O entitled memory capacity is selectively allocated based upon I/O demands of each I/O adapter.

Abstract: Active optics apparatus and method for aligning active optics are provided for a high-resolution, active optic fluorescence analyzer combining a large acceptance solid angle with wide energy tunability. A plurality of rows of correctors selectively controlled to bend an elongated strip of single crystal material like Si (400) into substantially any precisely defined shape. A pair of pushers engages opposite ends of the silicon crystal strip exert only a force along the long axis of the crystal strip, and does not induce additional bending moments which would result in a torsion of the crystal.

Abstract: A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When the received data value matches the stored cache data value, a first squash signal is generated. A received write address is compared with a reservation address. When the received write address matches the reservation address, a reservation signal is generated and inverted. The first squash signal and the inverted reservation signal are combined to selectively produce a silent store squash signal. The silent store squash signal cancels sending an invalidation signal.

Abstract: An infrared (IR) emission spectroscopy and microscopy apparatus with X-ray excitation or electron excitation and an improved process for extending spatial relation of infrared (IR) microscopy and performing microscopic infrared (IR) analysis by X-ray or electron radiation are provided. By utilizing nanometer sized X-ray beams or electron beams to produce IR emission, the spatial resolution of IR microscopy is extended. Simultaneously performing X-ray or electron-based spectroscopy as well as structural studies are enabled.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

Abstract: A method and apparatus are provided for implementing B-picture scene changes. A prediction stage predicts a B-picture scene change based upon a sequence of statistical information in an encoder order and a reaction stage is responsive to the prediction stage for modifying a quantization scale of a rate control algorithm.

Abstract: A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.

Abstract: Enhanced mechanical designs are provided for weak-link rotary mechanisms for implementing angular rotations with a defined angular travel range and positioning resolution, for example, with ten-degree-level travel range and ten-nanoradian-level positioning resolution. A weak-link rotary structure has a predetermined pattern for implementing angular rotations with repeatable and reliable angular travel range and positioning resolution including a plurality of connecting links radially extending from a central portion with a predefined angular separation between the connecting links; each said connecting link having at least one pair of weak-link connections; alternate connecting links being coupled to a respective terminal, each said respective terminal being mounted to a connecting carriage; remaining other connecting links being coupled to a respective mounting portion of a mating part of the weak-link rotary structure.

Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Abstract: A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff structure having a selected geometry is defined on the base SMT pad to increase thickness of the solder joint for the connector.

Abstract: Enhanced methods for separating of overlapping density porous materials are provided. The methods of the invention exploit the differences in the porosity of porous feed materials compared to that of the solid plastics. In the first stage, air is forced out of the pores of a porous feed material. In the second stage, a solution, having the appropriate density, is forced into the pores. This increases the density of the porous material relative to the density of the solid plastics. As a result, the porous material can be made to sink, while the solid plastics continue to float.

Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.