Abstract: A method and eFuse circuit for implementing enhanced security features using eFuses, such as disabling selected predefined test, debug, and mission security functions used in application-specific integrated circuits (ASICs), and a design structure on which the subject circuit resides are provided. The eFuse circuit includes a plurality of eFuses, a sense amplifier coupled to the plurality of eFuses, and a plurality of sense output latches coupled to the sense amplifier. The plurality of sense output latches is arranged to have a bias to power up to a known value. Control logic coupled to the plurality of sense output latches provides at least one predefined control signal responsive to the known value of the plurality of sense output latches, which enables a selected predefined security function. The plurality of eFuses is sensed and the ASIC is configured to a predefined state responsive to an applied POR/Sense control signal.

Abstract: Enhanced methods and a device enabling a plurality of tools for implementing a plurality of procedures for the accurate alignment and calibration of multiple components of the experimental set up at a synchrotron beam line are provided. The device includes an alignment pin or needle for centering a sample rotation axis. The device includes a YAG crystal for visualization of the beam and beam alignment and a metal foil for transmission or fluorescence measurements used for the monochromator calibration. The same, or different foils, or powders, or polymers, can be used for obtaining powder rings for finding the direct beam coordinates, for centering the beamstop on the direct beam and for calibration of the sample-to-detector distance.

Abstract: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.

Abstract: A prismatic lens and a reflector/refractor device having enhanced characteristics are provided for lighting fixtures. The prismatic lens and the reflector/refractor device are formed of a silicone material. A prismatic lens member includes a plurality of prisms on a surface thereof for refracting light. The reflector/refractor device includes a plurality of prisms on a surface thereof for reflecting and refracting light. The silicone material forming the prismatic lens and the reflector/refractor device is substantially transparent, and enables forming enhanced optical elements, for example, by injection molding technique. The silicone material is a selected one of dimethylsilicone, phenylmethlysilicone, or similar silicone material enabling enhanced optical performance for the prismatic lens and the reflector/refractor device.

Abstract: A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.

Abstract: A method and system to distribute high-power laser pulses to create sparks in individual cylinders of a multi-cylinder engine are provided. A laser provides laser output pulses. A distributor includes a linear array of mirrors with a respective mirror associated with one of the laser plugs. Each mirror is operatively controlled to move into a laser beam path to direct individual laser output pulses the associated laser plug for providing spark generation. The system enables correct cylinder firing order for predefined multi-cylinder firing sequences and allows for individual cylinder timing variation.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A method and apparatus are provided for scaling an input bandwidth for bandwidth allocation technology. An original bandwidth count value of an input flow is received. A bandwidth scaler constant is provided and used for scaling the received original bandwidth count value to provide a scaled bandwidth value between zero and one. The scaled bandwidth value is stored and used for calculating a transmit probability for the input flow.

Abstract: A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher and a design structure on which the subject circuit resides is provided. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.

Abstract: A method, apparatus and computer program product are provided for implementing virtual packet storage via packet work area (PWA) in a network processor system. A mapping area including a packet work area and a corresponding set of packet segment registers (PSRs) are provided. A PSR is loaded with a Packet ID (PID) and a packet translation unit maps the packet data into the corresponding PWA. The PWA address defining an offset into the packet is translated into a physical address. The packet translation unit redirects loads and stores of the PWA into the correct data buffer or buffers in system memory. Packets include one or more data buffers that are chained together, using a buffer descriptor providing the packet physical address. The buffer descriptor points to a data buffer for the packet and to a next buffer descriptor.

Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.

Abstract: A method and apparatus are provided for implementing bandwidth control in a communication link. A set link configuration for the communications link establishes a number of clock cycles required to transmit a data envelope. A control function aligns a start of a data packet on a fixed cycle boundary for data envelope transmissions. The control function aligns the start of a data packet in the same byte of the 16 byte field. The control function is implemented with a memory management input/output (MMIO) register and a counter, and allows a transmitting side of the communications link to control the pacing of data packet transmission or bandwidth by aligning all data packets on fixed-cycle boundaries.

Abstract: A biosensor utilizing bio-functionalized magnetic nanoparticles is provided. An external magnetic field is applied to a suspension of magnetic nanoparticles. A linearly polarized incident light is applied to the suspension of magnetic nanoparticles. A photocurrent from polarized light scattering by bio-functionalized magnetic nanoparticles in liquid is detected. The magneto-optic sensing technique is applied to a micro-fluidic channel for rapid and sensitive detection with a small sample amount, and subsequent magnetic separation for detoxification. This technique is used for the detection of Brownian relaxation with time sweep as well as frequency sweep. The magneto-optical sensor enables rapidly detecting changes in local dynamic properties of the magnetic nanoparticles in liquids and magnetic modulation of ferromagnetic particles in liquid provides increased signal sensitivity.

Abstract: A bipolar plate supported solid oxide fuel cell with a sealed anode compartment is provided. The solid oxide fuel cell includes a cathode, an electrolyte, and an anode, which are supported on a metallic bipolar plate assembly including gas flow fields and the gas impermeable bipolar plate. The electrolyte and anode are sealed into an anode compartment with a metal perimeter seal. An improved method of sealing is provided by extending the metal seal around the entire perimeter of the cell between an electrolyte and the bipolar plate to form the anode compartment. During a single-step high temperature sintering process the metal seal bonds to the edges of the electrolyte and anode layers, the metal foam flow field and the bipolar plate to form a gastight containment.

Abstract: An automated scanning system and method, utilizing specialized dual phased array ultrasonic transducers for producing and detecting Rayleigh waves in ceramic bearing balls are provided for nondestructive, non-contact inspection of ceramic bearing balls. The phased array ultrasonic transducer utilizes a complex curvature configuration that enables the dual phased array ultrasonic transducers to focus ultrasonic energy onto the ball to optimally generate and receive Rayleigh wave signals in the spherical objects.

Abstract: A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.

Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.