Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract: A system and related method for automating alert decision-making in a computer network are disclosed. The system and method act to receive an alert request from an event management system, and then carries out operations using several sets of inference rules, associating the alert request to a generic conceptual data model of alert request and alert resolution. The generic model is specialized to represent the specific environment being monitored. The alert request is enriched with contextual and network information in order to generate one or several alert resolution actions.

Abstract: A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive sequence of all method calls in different classes or their instances that are invoked by said selected method in said selected class. A Sequence Diagram is generated from said Call Tree. The tool remembers all updates to the Call Tree used to generate the Sequence Diagram. This information is used when a generated Sequence Diagram is impacted due to changes made to any source code file included in the project.

Abstract: A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive sequence of all method calls in different classes or their instances that are invoked by said selected method in said selected class. A Sequence Diagram is generated from said Call Tree. The tool remembers all updates to the Call Tree used to generate the Sequence Diagram. This information is used when a generated Sequence Diagram is impacted due to changes made to any source code file included in the project.

Abstract: A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive sequence of all method calls in different classes or their instances that are invoked by said selected method in said selected class. A Sequence Diagram is generated from said Call Tree. The tool remembers all updates to the Call Tree used to generate the Sequence Diagram. This information is used when a generated Sequence Diagram is impacted due to changes made to any source code file included in the project.

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved.

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Abstract: A method and apparatus for selecting a client computer as a relay server to rebroadcast common application information that is broadcast from a server system over a network. The client computer is selected randomly to rebroadcast the User Datagram Protocol (UDP) information received from the server system and client computers receiving the UDP information from another client computer relay server on the network do not rebroadcast the information. If the client computer selected to rebroadcast the common information fails to rebroadcast, another client computer is randomly selected as a relay server and takes over rebroadcasting the common information.

Abstract: Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening to maintain the polished surface at the TSV structures and, thus, reliable conductivity to the BSM layer.

Abstract: There is disclosed a double-sided liquid crystal display (LCD) panel which includes a first polymer dispersed liquid crystal (PDLC) layer configured to be responsive to an applied DC voltage for making the first PDLC layer substantially transparent; a center liquid crystal cell layer; a second PDLC layer configured to be responsive to an applied DC voltage for making the second PDLC layer substantially transparent; and an LCD control module configured to control the first and second PDLC layers such that the center liquid crystal cell layer is viewable from a selected viewing side. Depending on the selected viewing side, the LCD control module is configured to select one of the first and second PDLC layers to make substantially transparent, and the other of the first and second PDLC layers to make substantially translucent. A light source may be applied to a side of a translucent one of the PDLC layers to provide a backlight for the center liquid crystal layer.

Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.

Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

Abstract: A system, program product and method for automatically adjusting the traffic light of a traffic light controlled intersection. Personal data relative to a pedestrian cross walking the intersection, including walking speed, and the current speed of a vehicle approaching the intersection are simultaneously acquired. Both the personal data and the vehicle current speed are processed to generate cross walk control signals, such as indicators of risk of collision between vehicle and pedestrian. Where the risk warrants action, the “stop” condition of the traffic light is enable to warn the vehicle to stop. Traffic control signals are also generated to control the duration of the “walk” condition for slow moving pedestrians.

Abstract: An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.

Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.