Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench.

Abstract: A coaxial connector having a conductive copper wire core plated with a layer of gold with the layer of gold surrounded by a dielectric layer, such as polyimide. The layer of polyimide is surrounded by a conductive shielding layer, such as copper, with a tin-plated layer surrounding it. Connection of the coaxial connector at one end to adjacent signal and ground pads is achieved by laser ablation to expose a section of gold sufficient to accommodate the terminal pad pitch and allow wire bonding to the signal pad. Connection of the conductive shielding layer to the ground pad is achieved by hot tip soldering. Connection at the opposite end of the coaxial connector uses the same process.

Abstract: An electrical connector arrangement for connecting electronic devices to one another. The connector arrangement uses tensile members and compression members, at least the tensile members of which act to provide both an electrical connection between electronic devices and force over a range of distances to hold the devices together. The tensile members provides tensile force acting to hold the electronic devices together while the compression members provide an opposing compressive force over a range of distances which balances the tensile force to thereby form a cellforce connector used to connect an array of electrical contact points on one electronic device to a corresponding array of electrical contact points on another electronic device.

Abstract: An electrical connector or interposer for making connection in a high density device electronic environment. The connector is made of a high density array of nickel columns held in a layer of polyimide with each column extending beyond the opposing surfaces of said layer of polyimide. The connector may be used to make temporary or permanent connection to electrical contacts without alignment. Connection may be accomplished by loading forces sufficient to form either an indentation or a penetration of solder ball contacts. Contact to a single chip or a full wafer of chips is facilitated for testing.

Abstract: The buckling beam probe contactor assembly comprises a number of square test probe arrays each containing a plurality of buckling beams in the form of continuous wires extending from the probe tips to a remote test apparatus. The buckling beams pass through an adjustable beam carrier block and through a number of guide plates which are kept in predetermined distances along the buckling beams by means of thin stabilizing rods arranged at the corners of the test probe array. The guide plates are inserted into grid-like frames which allow the arrangement of a plurality of test probe arrays close to each other wherein each array may contain test probes over its full area except for the locations occupied by the thin stabilizing rods.

Abstract: A telephone pay station wherein a disconnect circuit is provided for disconnecting the pay station from the central office in response to the coin collect signal generated at the central office.

Abstract: Apparatus in a vacuum deposition system positions a workpiece holder in substantial alignment with a source of material to be deposited onto a work piece affixed to the workpiece holder. The apparatus also rotates the workpiece holder about the deposition source and linearly drives the workpiece holder to varying distances from the deposition source. The apparatus used to drive the workpiece holder is sealably mounted atop an opening in the vacuum chamber. The apparatus enables multiple source depositions to be carried out consecutively without accessing the vacuum chamber. By aligning the workpiece holder over the deposition source, nonuniform deposition onto the workpiece is substantially eliminated.

Abstract: This invention relates to a circuit for holding a pulse at an up level during a time interval .tau. after the input signal has been removed, and to the use of the circuit to realize a monostable multivibrator. The holding circuit features a bipolar transistor that is driven into saturation by the application of an input signal in the form of a clock pulse. The hold circuit also features a control network including a diode and a drain resistor. Upon removal of the input signal the charge stored in the base of the saturated transistor is caused by the diode to flow in a controlled manner to the drain resistor so that the transistor is cut off after a time interval .tau. closely approximating the storage time t.sub.s. Thus, the holding circuit provides a pulse of width T+.tau.. A monostable multivibrator is obtained by connecting the holding circuit to one of the two inputs of a conventional NOR circuit. The other NOR circuit input receives the input clock pulse.

Abstract: A method and apparatus for forming multilayer ceramic substrates from large area ceramic green sheets, each having an array of layer sites thereon, by serially aligning each individual layer site with respect to a die cavity and punching the aligned layer site into the die cavity to thereby stack the requisite number of aligned layer sites. Individual layer site alignment ensures that each layer site is aligned with respect to the die cavity so that the dimensional tolerances between layer sites on the large area green sheet are eliminated. Thus, as large a green sheet as is cost effective may be employed, notwithstanding the fact that dimensional distortions on the large area green sheet would preclude alignment of corresponding layer site vias on superimposed large area green sheets.

Abstract: A method is taught for repairing pinholes in dielectric layers and thereby avoiding metal shorts. The method is applied after the dielectric has been deposited on a base of conductive metallurgy and involves heating the metal-dielectric layers in an oxygen ambient and thereby oxidizing any exposed metal. The metal-oxide formed in the pinhole effectively insulates the underlying metal from a subsequently deposited metal; and, hence acts to prevent metal-to-metal shorts.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing appropriate dopant material into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: A non-volatile semiconductor memory and switching device employing a Schottky barrier junction and a dual layered dielectric system for entrapping charges adjacent thereto. The dual layered dielectric system typically comprises a layer of nitride on a layer of oxide arranged such that trapped charges within the oxide and at the nitride-oxide interface act to alter the depletion region beneath, and in the vicinity of, the Schottky contact. Trapped charges may be made to selectively modify the Schottky barrier depletion region and vary its conductivity characteristics between a diode characteristic (OFF) at one extreme and ohmic contact (ON) at the other, all in accordance with the magnitude and sign of the trapped charges.

Abstract: A method and electronic network for limiting the electrical noise arising during transmission of digital data signals from a first integrated circuit having multiple output devices at which the data signals are formed to the input of a second integrated circuit. The method and network feature steps and means for sensing the conduction state of the first integrated circuit devices and for generating a control signal to invert the data signals before transmission when the number of output devices conducting is equal to or greater than a predetermined number. The method and network also feature steps and means for transmitting the data signals and control signal so that the data signals may be reconstituted to establish the data signals as they appear at the first integrated circuit output, before the data signals are presented to the second integrated circuit input.

Abstract: A method for etching a batch of semiconductor wafers to end point using optical emission spectroscopy is described. The method is applicable to any form of dry plasma etching which produces an emission species capable of being monitored. In a preferred embodiment, as well as a first alternative embodiment, a computer simulation is performed using an algorithm describing the concentration of the monitored etch species within the etching chamber as a function of time. The simulation produces a time period for continuing the etching process past a detected time while monitoring the intensity of emission of the etch species. In a second alternative embodiment, this latter time period is calculated using mathematical distributions describing the parameters of the etching process. In all three embodiments, the actual time that end point of an etching process is reached is closely approximated.

Abstract: An integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region into and out of the capacitive storage region. Each memory cell also includes an offset contact region which contacts an adjacent bit line. The word lines are arranged in rows and the bit lines are arranged in columns, complementary pairs of bit lines being electrically connected to alternate ones of memory cells along each column. A bit line to diffusion capacitance couples each memory cell to the one of the pair of bit lines to which it is electrically not connected. This capacitance boosts the electrical signal written into and read out from the storage capacitor.

Abstract: A micro dispense valve arrangement for accurately dispensing minute quantities of a fluid. The valve arrangement interfaces an enclosed interior region under pressure with an exterior region of less pressure through an orifice opening. The orifice wall is tapered from interior to exterior to bound a frustoconical region constricting toward the exterior to accommodate a magnetizable pellet or ball. The ball is held in its seated position against the orifice wall by permanent magnets imbedded in the wall. An AC coil surrounding the orifice opening acts when energized to cause the ball to move between its seated or closed position and a non-magnetizable screen in its open position. The frequency and duration of applied positive and negative pulses driving the coil act to control the on/off fluid flow duty cycle of the valve.

Abstract: Disclosed is a high performance current switch push-pull driver circuit. A first output of the current switch is direct coupled to the push-pull driver while the second output of the current switch is coupled to the push-pull driver by means of an emitter follower and current mirror. Emitter followers connected to the current switch provide a first pair of true/complement outputs while push-pull drivers provide a second set of true/complementary outputs having a higher drive capability. The current mirror is biased near its turn on potential providing current control switching of the current mode transistor and the push-pull driver transistor with which it is coupled. The circuit is greatly tolerant for varying load conditions, is protected against short circuit and power supply failures and has means for three state operation.

Abstract: Disclosed is a memory array in which each cell consists of a pair of cross coupled bipolar transistors with antisaturation clamps, a load resistor connected to the collector of each of the cross coupled transistors forming storage nodes, and Schottky barrier diode input/output devices connecting each node to a respective bit line. The emitters of the cross coupled transistors are connected to a lower word line while the load resistors are connected to an upper word line. Both the upper and lower word lines are switchable providing high speed as well as highly stable operation with very low power supply voltage requirements.

Abstract: This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

Abstract: In the fabrication of Schottky barrier diodes, in conjunction with active devices such as transistors, it has become the conventional practice to use reactive ion etching (RIE) to remove a protective layer of Si.sub.3 N.sub.4. This step of etching is used in forming the anode regions of the Schottky barrier diodes, as well as the active device regions of the transistors. It has been discovered by the present inventors that "resistive shorts" which have been produced in this context--thus ruining the Schottky barrier function--result from the fact that pinholes in the underlying oxide insulating layer permit the reactant gas to etch all the way down to the silicon substrate so as to produce diffusion paths or "pipes" through the oxide. Accordingly, instead of the oxide layer acting to block diffusion in the Schottky anode areas, these diffusion paths permit the resistive shorts to be formed. The present invention involves the use of a low energy collimated ion beam in an inert atmosphere, e.g.