Abstract: A reactive ion etching chamber structure is designed to provide operation with uniformity in electric field and generated plasma so as to produce uniform, contaminant-free etching over large batches of silicon wafers. The anode chamber structure is cylindrical and physically symmetrical with respect to a round cathode plate with the internal surfaces of the chamber being free of any apertures, holes, recesses, or the like, having an opening dimension larger than one tenth the thickness of plasma "dark space". Under normal reactive ion etching conditions, such opening dimension is 1.5 mm or less and the distance between cathode and anode internal surface is 3.0 mm, or less.

Abstract: An electron beam projection system having a projection lens arranged so that upon pre-deflection of the electron beam the electron optical axis of the lens shifts to be coincident with the deflected beam. The projection system includes means for producing an electron beam, means for deflecting the beam, a magnetic projection lens having rotational symmetry for focusing the deflected beam and a pair of magnetic compensation yokes positioned within the bore of the projection lens means. The pair of correction yokes has coil dimensions such that, in combination, they produce a magnetic compensation field proportional to the first derivative of the axial magnetic field strength distribution curve of the projection lens. Upon application of current to the pair of compensation yokes the electron optical axis of the projection lens shifts to the position of the deflected beam so that the electron beam remains coincident with the shifted electron optical axis and lands perpendicular to a target.

Abstract: An in situ thickness change monitor for determining thickness change in opaque product material, such as silicon, in chamber apparatus, such as reactive ion etching apparatus, operative to produce such thickness change. Reference material having thickness change properties, such as etch-rate, correlatable to the product material thickness change properties is deposited upon a substrate having an index of refraction such as to form a monitor exhibiting an optical discontinuity. With the monitor positioned within the chamber with the product material, light directed thereto acts to provide reflected beams producing light having an intensity variation due to interference indicative of the thickness of the reference material. Changes in the thickness of the reference material are correlated to changes in thickness of the product material.

Abstract: As etching progresses from one layer of material to another in reactive ion etching systems, the partial pressures of the reaction chamber gas components change. In constant pressure reactive ion etching systems, changes in chamber pressure are corrected by changes in the etchant species flow rate into the reaction chamber. By monitoring flow rate, information is obtained which may be used to identify the points where partial pressures change, and latter may, in turn, be used to derive etching points in the material being etched.

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.

Abstract: A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

Abstract: A batch chip placement system for batch positioning semiconductor chips, or the like, upon a substrate containing an array of chip sites or footprints whose actual position on the substrate deviates from the theoretical or nominal position over successive substrates. The positioning is achieved by first sensing the X and Y offsets of a pair of alignment marks on the substrate from their theoretical or nominal position to determine the .DELTA.X and .DELTA.Y correction factors required to obtain the actual X,Y position of the alignment marks. The actual X,Y position of the alignment marks is used to determine actual X,Y chip position values, .theta. rotation and shrinkage factor corrections required to obtain proper orientation and positioning for batch chip placement.

Abstract: A plasma enhancing baffle plate is employed in conjunction with the anode of an RIE system to provide uniform silicon etching. The baffle plate is conductively coupled to and provided in relatively close proximity to the anode to form a constricted chamber region between anode and baffle plate. With the constricted chamber open to the RIE chamber through aperture means in the baffle plate the total surface area of the anode is increased, such that when the system is biased to operate in an RIE mode an increase in the generation of neutral etching species is effected. Various aperture arrangements may be employed to provide different patterns of neutral etching species generation, in accordance with the peculiar characteristics of the system employed.

Abstract: An interface circuit for exchanging digital signals between two pieces of data processing equipment is provided in integrated form in accordance with international standards, such as EIA Standards. This is achieved through modification of an operational amplifier to adapt its use to the conditions and requirements of interface circuits.

Abstract: Bipolar transistor devices are formed by employing polysilicon base contacts self-aligned with respect to a diffusion or ion implantation window used to form emitter, intrinsic base and raised subcollector regions. The polysilicon acts as a self-aligned impurity source to form the extrinsic base region therebelow and, after being coated with silicon dioxide on its surface and along the sidewalls of the diffusion or ion implantation window, as a mask. Directional reactive ion etching is used to form a window in the silicon dioxide while retaining it along the sidewalls. Ion implantation, for example, may be used to form, through the window, an emitter, intrinsic base and raised subcollector region. The silicon dioxide is used as an insulator to separate the emitter contact from polysilicon.

Abstract: In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor switching means are coupled to each bit line to provide a discharge path for the line capacitances associated therewith. Common transistor switching means are coupled to each individual bit line transistor switching means to commonly discharge the individual discharge currents received from each individual bit line transistor switching means. Individual word line transistor switching means are also connected to respective word lines to distribute the current passing through the common transistor switching means to the respective word lines. The discharge circuit arrangement permits minimum-area bit line and word line transistor switching means.

Abstract: Arrangements are described for correcting the voltage coefficient of resistance (VCR) of resistors integral with a semiconductor body and, more particularly, for correcting the VCR of resistors implanted in a semi-conductor body. Resistors typically comprising a resistive region of a first conductivity type formed in an isolated layer of opposite conductivity type which isolated layer, in general, includes an epitaxial layer passivated by a dielectric layer. A metal layer is formed on the dielectric layer and covers, at least partially, the resistive layer. The metal layer is brought to a suitable potential to produce opposite variations in the resistance with respect to variations created by the epitaxial layer.

Abstract: An open diffusion method of doping a silicon body with boron. In a first open diffusion heating step, a boron glass is deposited upon the silicon body with a silicon-rich boron phase (SiB.sub.6) formed beneath the glass where deposition is directly on silicon. The boron glass and SiB.sub.6 layer are formed by exposing the silicon body to a gas mixture containing a predetermined boron quantity and boron and oxygen in a predetermined quantitative ratio. Etching steps then permit the removal of the boron glass without deleteriously affecting the SiB.sub.6 layer or underlying silicon, or uncontrollably affecting any SiO.sub.2 masking layers. In a second heating step, at least a part of the boron from the SiB.sub.6 layer is driven into the silicon in an inert or oxidizing atmosphere.

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.

Abstract: A rotating target ion bombard or implant apparatus with an arrangement for cooling the target. The cooling arrangement utilizes a pattern of air openings or passages and air fins. The pattern of air openings are positioned concentric to the disc hub and act to separate the hub region of the disc from the outer target or work region. The air openings function to both reduce the conductive cross-section between the hub region and outer work region of the disc and permit air to pass from the implant or bombard side to the back surface thereof. The air fins are provided on the back surface of the disc to draw air through the openings when rotating. Cooling is achieved by rotating in atmosphere during the load/unload cycle of operation. Reduction of the conductive cross-section between work region and hub region reduces heat transfer to the ferrofluidic feedthrough means coupled to the hub region thereby increasing the ferrofluidic feedthrough means lifetime.

Abstract: A method and apparatus for modifying a surface, by either plasma etching the surface or plasma depositing a material thereon, by using vacuum ultraviolet radiation to control the modification of the surface.

Abstract: Process and apparatus for use in extracting negative ions from a plasma which is particularly useful in reactive ion etching of metals, silicon and oxides and nitrides of silicon in the manufacture of semiconductor devices. A magnetic field is employed in the apparatus and, herein, is created by a novel grid, through which negative ions pass to a surface, such as one to be etched, while free electrons are prevented from passing through the grid and out of the plasma. The novel process utilizes negative ions which have a large fraction in the atomic state.

Abstract: A light pen detection and tracking scheme for detecting and tracking both "on" and "off" cells with a single cursor voltage waveform in an AC gas discharge display panel. The special cursor voltage waveform is applied to the panel during the sustain cycle, in either a line-by-line or binary scanning fashion, to momentarily fire both "on" and "off" cells so that they may be detected by the light pen without a loss of the memory state of the cells. A cross-hair cursor is automatically displayed at the pen position when the search scan is complete. Since both "on" and "off" cells are detected, the system can respond to pen motion by repeating the search to reacquire the pen, so that no special tracking strategy is needed.

Abstract: The construction of the dielectric layer of a panel used in making a gas panel display by an E-gun evaporation process in the same evacuated chamber that deposits an electron-emissive layer on the panel so as to obtain increased efficiency in the fabrication and improved operating characteristics of the gas panel. Stress free dielectric layers are obtained by E-gun evaporating borosilicate glass from a molten pool of borosilicate having an area of at least 2cm.sup.2 up to about 10cm.sup.2 with the substrate for the layers being maintained at from 200.degree. C to 300.degree. C and the evaporation rate being 40 to 80 A/sec. at approximately 10 inches from the molten pool.

Abstract: Improved writing and erasing in AC gas discharge display panels is obtained by applying a special normalizing voltage waveform to cause the cells to be in a more standardized state, so that the applied writing and erasing pulses act to cause wall voltage changes which are less sensitive to the cell's recent history. The special normalizing waveform is applied adjacent to the erase pulse and/or to the write pulse and acts to fire the cells in a manner such that there is no loss in the memory state of the cells.