Abstract: A digital programmable ultrasonic generator for driving an ultrasonic transducer includes a computer for receiving and storing a plurality of selectable programs. The programs are indicative of different modes of operation. A profile generator is coupled to the computer to receive programs and to produce a digital reference voltage indicative of a voltage profile to be generated for the mode selected. A digital frequency controller is coupled to a direct digital synthesizer for producing a predetermined frequency in response to a programmed frequency command from the computer. A process controller receives the output of the direct digital synthesizer as a voltage signal having the desired frequency and modifies the voltage depending on the mode of operation and voltage desired before driving a power amplifier coupled to the transducer to be driven.

Abstract: Apparatus is provided for transferring user defined data from a parallel storage medium to a serial link driver in an I/O channel subsystem of a processor or I/O device controller. The serial link driver transmits a frame of user defined data over a serial data transfer medium. A data buffer receives and stores user defined data from the parallel storage medium. A control data facility that is distinct from the data buffer forms and transmits control data from the sender of the frame to the recipient of the frame via a path that does not include the data buffer. The control data facility includes respectively different dedicated logic for asynchronously generating each of the following: special character sequences, frame delimiters, headers, and cyclic redundancy checksums. A switching facility receives the user defined data from the data buffer. The switching facility also receives control data from the control data facility.

Abstract: A method and apparatus enables a newly installed peripheral device such as a disk device to be used with a computer system without changing the operating system. The peripheral device is identified as a type which is not recognized by an operating system operating in conjunction with the computer system. A value which identifies at least one logical attribute of said peripheral device is obtained from said peripheral device. A determination is made as to whether the operating system and the peripheral device are compatible based on the logical attribute obtained from the peripheral device. The operating system and the peripheral device communicate if it is determined that the operating system and the peripheral device are compatible (i.e., can operate together).

Abstract: A system and method are disclosed for providing computers, particularly the Unisys A series computers, with the capability to function with disk drives of more than one sector format, especially if a predetermined sector format is inefficient and/or cost prohibitive. Interfacing is provided for processing I/O requests between a predetermined logical sector format (e.g., 180 byte sectors) and a variable physical sector format (e.g., 512 or 720 byte sectors). Read operations compare read request addresses to physical sector boundaries and discard unwanted data. Write operations, using at least one sector buffer, perform a read/modify/write cycle, such that the necessary physical sector data not associated with the write request is read into the sector buffer, modified and written back to the disk along with the write data inserted at the appropriate location. This system and method can effectively increase the usable capacity of selected disk drives by 15-20%.

Abstract: The present invention comprises an improvement of a known bi-directional linear motor and is applicable to other linear motors. The linear motor comprises a plurality of pole pieces arranged as a closed frame having three horizontal pole pieces and two vertical end pieces with permanent magnets mounted therein to form a closed stator core having a symmetrical permanent magnetic flux field path in the stator. A force coil is mounted over the center pole piece of the three horizontal pole pieces. When force current is applied to the force coil a reaction flux is generated in the stator core which creates an unbalanced flux field in the stator core. At least one air gap is provided in at least one of the pole pieces through which the reaction flux passes to increase the magnetic inductance which in turn increase the force on the force coil for a given force current.

Abstract: Disclosed is a telephony messaging transfer system permitting a messaging host to redistribute its processing and/or storage load to another messaging host. An administrator can dynamically control the amount of time needed to transfer specified mailboxes by monitoring the progress on-line and increasing or decreasing the number of transfer dialogs to be used in the transfer process. Also provided is a predictive simulator for simulating the transfer process and providing statistics that can be used to adjust the timing of the actual transfer.

Abstract: A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the HFS 9009 for bench top testing. The process, which in the exemplary embodiment is implemented in software, accepts various parameters as inputs (e.g., channel name(s) for stimulus generator, range of vectors, etc.) for purposes of extraction and translation. The process provides an Interface and Initialization Unit (IIU) and a Translator Unit (TU). The IIU provides a user interface necessary for a user to select the various options available. In addition, the IIU coordinates the use of memory, file I/O and communication with the active files on the off-bench tester. The IIU verifies user selections and does error checking. Once complete, the TU translates the selected signals for the vector range entered by the user.

Abstract: An integrated combined heating and cooling unit comprises a known high efficiency gas fireplace unit stacked on top of a known high efficiency window type air conditioning unit. Novel vent adapters are connected to the rear of the units for connecting them to a source of outside combustion and cooling air to effect high efficiency operations. Novel controls comprise a fireplace relay and an air conditioning relay mounted inside of each of the units. The relays control the on-off operation of the respective units and are actuated by a thermostatic control preferably located remote from the combined units.

Abstract: A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer.

Abstract: A system and method for automatically detecting the presence and configuration (e.g., number of rows and columns) of a writable memory module. A first data pattern is written to a first memory location. One or more data patterns different from the first data pattern are written to a second and subsequent memory locations in a walking-one sequence. After each write to the second and subsequent memory locations the data pattern at the first memory location is read. The read data pattern is compared to the first data pattern to determine if the first data pattern has been overwritten. The first data pattern is overwritten when the number of memory locations has been exceeded.

Abstract: A video controller that enables applications operating in a protected, multiprocessing system to update a video memory at native speeds. In this system and method, each application is assigned a separate physical address region that identifies an alias of an application's window in the video memory. The separate physical address regions provide an addressing mechanism for an application to identify a referenced set of pixels sought to be accessed. A window mapping function within the video controller that performs only those portions of a video memory access request that references pixels contained within a visible portion of an application's window as defined by priority, size and position information in a control structure.

Abstract: A low radar cross section lens antenna having high gain is disclosed. A spherical lens having a dielectric radial gradient focuses planar RF energy coupled thereto onto a focal point on the surface of a lens located diametrically opposite from the first intersection of the plane wave and the lens. The lens partially encloses a wedge shaped RF absorbing portion having the edge of the wedge passing through the center of the lens. The lens is partially surrounded by a second RF absorbing portion having a bowl-like shape. An antenna feed having its aperture located adjacent the surface of the lens is mounted to rotate about an axis lying substantially along the edge of said wedge shaped absorbing portion. Elevation rotation means is provided to rotate the feed antenna within a slot contained within the second RF absorbing portion.

Abstract: A versatile surround trim mounting device comprises an extruded metal surround trim piece formed as three separate legs and joined together to form a U-shaped frame structure. The extrusion comprises a pair of parallel trim edges that are separated from each other by a connecting recessed tile support therebetween. The recessed tile support is further provided with two side support structures. A spring bias force is placed against one of the side supports to urge a tile to lock it against the opposite side support so that the versatile surround trim appears to the eye be horizontal and vertical rows of decorative tiles surrounding a prefabricated fireplace.

Abstract: In a high speed main frame computer system, a high speed instruction processor is provided with a high speed cache memory. The cache memory is provided with a plurality of associated memories including a tag memory. Every time the instruction processor attempts to access the cache memory, a cache set address is generated which accesses the associated memories to provide most recently used (MRU) block information, validity information and degrade block information. The accessed information is applied as inputs to a cache logic system. The cache logic system logically modifies the information to generate an update of the MRU information and writes the modified MRU information into the MRU associated memory at the set address without control or supervision on the part of the instruction processor. The cache logic system also generates the least recently used (LRU) block coded information using the MRU information, validity information and degraded block information for cache block replacement.

Abstract: In a spread spectrum multipoint-to-point communication system there is provided a novel frequency to phase converter, for automatically synchronizing the PN codes of the user transmitters/receiver with the receiver/transmitter in the central hub. The highly accurate frequency to phase converter generates a highly accurate phase error signal for synchronizing the multiuser network. The frequency to phase converter includes a serial adder and a series to parallel converter and a shift register which integrates the highly accurate phase error signal values and produces a highly accurate frequency value which is applied to the input of the resident processor in the central hub transmitter/receiver. The central hub transmitter/receiver calculates the clock offset for synchronizing each of the user receiver transmitters and generates a clock adjusting signal which is transmitted to the user receiver/transmitters.

Abstract: Apparatus and method are provided for adaptively modulating or combining a first signal with a second signal. A series of values of the first signal are taken and sequentially stored in a shift register. The maximum absolute value of the oldest N values (where N is an integer) stored in the shift register is then determined. Before, during or after that determination, the maximum absolute value of the remaining (newer) series of values of the shift register is also determined. The lesser of those two maximum absolute values is then determined. This lesser maximum absolute value is then multiplied by a gain factor representing the desired gain to produce a scale factor. The gain factor can be a preset constant, or can be based on the steady-state ratio of the power of the second signal to the power of the first signal. The second signal is then multiplied by the scale factor to produce a scaled signal.

Abstract: A quiescent test circuit for interfacing a high precision integrated circuit tester to a device under test (DUT). The quiescent test circuit is capable of supplying a high powered (V1) voltage supply to a DUT while the DUT's desired dynamics internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously which deselects the high-powered (V1) voltage supply to the DUT and selects the integrated circuit tester's parametric measurement unit low power (V4) voltage supply for powering the DUT. The integrated circuit tester, through its parametric measurement unit is capable of precisely measuring the very low quiescent current of the DUT, while powering the DUT.

Abstract: A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Abstract: A novel container is provided for holding fragile wire bonding capillaries which comprises two parts, one being a resilient cap and the other being a cover which allows the capillary to be transported therein. The resilient cap comprises a first outer connector on the base for receiving a cover and comprises a second inner connector for receiving a capillary therein. The inner connector is further provided with a gage surface for mounting the capillary in a transducer at a proper working height without removing the capillary from the container cap. Further, the novel cap is provided with vertical slots in the inner and the outer connectors which permits the cap to be moved horizontally to remove the capillary from the cap without harming the fragile tip of the capillary.

Abstract: Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.