Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Abstract: A self-isolated Schottky Barrier diode structure and method of fabrication are disclosed for generating a device having controlled characteristics. An opening is made through an oxide layer over a central region of an n-type semiconductor substrate. The opening has inclined sidewalls over an annular region surrounding the central region of the substrate. An n-type dopant layer is ion implanted through the opening and the surrounding oxide layer. This controls the barrier height for the Schottky Barrier diode. In the region of the substrate surrounding the annular region, where the ion implantation takes place through the full thickness of the oxide, the lifetime of minority carriers is controlled. This has the effect of minimizing PNP parasitic transistor action. A Schottky Barrier contact is formed in the opening through the oxide layer creating a rectifying junction with the semiconductor substrate in the central region.

Abstract: A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.

Abstract: A method and apparatus are disclosed for acquiring transmit synchronization at a secondary station with the periodic frame reference bursts from a reference station in a TDMA network in an improved manner to enable the use of full power initial acquisition bursts while also reducing the bandwidth required to complete the initial acquisition operation. During the first phase, the apparatus at the secondary station bursts an initial acquisition burst during a relatively wide interval in the traffic portion of a TDMA frame and measures a propagation delay factor. The apparatus then adds the propagation delay factor to the receive frame timing synchronized with the reception of the frame reference bursts at the secondary station to obtain a more accurate adjusted transmit frame timing.

Abstract: A bipolar compatible electrically alterable read-only memory device and process are disclosed based upon the formation of an aluminum gate structure on the surface of a thin oxide layer in an FET precursor device, wherein the aluminum gate structure serves both as an ion-implantation blocking mask for forming self-aligned source and drain regions and, in addition, a source of aluminum for the solid state reaction between the silicon dioxide layer and aluminum, forming an aluminum oxide/silicon dioxide composite charge storage region. The process is wholly compatible with existing bipolar processing technologies so that high speed bipolar support circuitry can be utilized on the same semiconductor chip with the programmable device disclosed. The programmable device disclosed has the unique advantages of having a programming voltage which can be tailored to substantially match the signal voltages on the rest of the chip by controlling the solid state reaction for the aluminum oxide formation step.

Abstract: A multiple data rate digital switch for a TDMA communications controller is disclosed which can service a plurality of input/output ports having many different data rates on a time divided basis, either between ports connected to the same controller or between ports connected to different, geographically remote controllers. A transmit burst buffer and a receive burst buffer are connected between the local ports and a TDMA communication link and an intranodal buffer is connected between local ports. All three buffers are accessed by a switch control memory which stores n.sub.i control words for each of the ports which are scanned m times per TDMA frame, there being a frame rate of f frames per second. Thus, the ports are selected and their data is buffered at a rate R.sub.i which is equal to the product of n.sub.i times m times f. In this manner, ports having a variety of data rates can be serviced on a time interleaved basis with maximum connectivity.

Abstract: The position of a channel of information transmitted from a particular port is varied in response to the changing priority of that port's messages as time passes. Variable priority assignments become necessary when low speed data has been deferred in its transmission until a time just prior to the production of a second unit of data. The effect of changing the priority of deferred data messages in a TDMA burst is to change the relative position of the associated channel within the TDMA burst by means of compiling the address of that message in a higher priority threaded list.

Abstract: A semiconductor fabrication process and the resulting structure is disclosed for an FET device with a precisely defined channel length. Two process embodiments are described to make a diffused MOS device which does not require the use of p-type diffusions to obtain 1 micron channel length. Instead, to accurately define such micron-range channel lengths, a lateral etching technique is employed. To obtain well controlled threshold voltages, the channels are ion implanted. Thus the enhancement portion of the diffused MOS device channel is defined by an etching step instead of a diffusion step, thereby producing a channel having a length which is shorter and a threshold voltage which is better controlled than those which have been available in the prior art.

Abstract: A control architecture is disclosed for a communications controller, for connecting a control processor in the communications controller to a plurality of internal processing subunits which operate asynchronously at different data rates. The architecture includes a control adapter which is connected between the control processor and a common subunit bus, for receiving from the control processor, a control command, a plurality of data words, and an associated address for a respective one of the processing subunits. The control adapter outputs an operating code and the plurality of data words on the common subunit bus and further outputs a subunit select signal on a respective subunit select line to the subunit designated in the address. The adapter further includes a memory for storing the number of shift intervals to be applied to a stack shift signal which is output on a stack shift bus which is common to all of the subunits.

Abstract: An improved I.sup.2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and reduces the emitter diffusion capacitance in the upward injecting vertical NPN transistor and reduces the minority carrier charge storage and increases the collector efficiency in the lateral PNP transistor.

Abstract: In a time division multiple access satellite communication system, a reference station which allocates channel capacity also regulates demand by the ground stations for that capacity. The regulation is accomplished by means in the reference station for transmitting limiting, blocking and revocation messages to the ground stations and means in the ground stations responsive to these messages to regulate the processing of input service requests. The limiting messages notify the ground stations to limit their channel usage to the channels required in the last demand message transmitted but not to exceed their last channel assignment. The blocking messages instruct the ground stations to unconditionally block any new requests for service on their input ports, rather than counting such calls as increments of demand, and thereby effectively reduce the aggregate demand in the system.

Abstract: The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This eliminates the necessity for bit stuffing to accommodate non-integral multiple data rate data ports and yet allows data activity compression operations to be carried out.

Abstract: To make the most efficient use of the TDMA frame for a satellite communications network, the assignment of each local station's TDMA burst duration is based on a statistical assessment of the demand by local voice and data ports. Occasionally the actual voice and data port demand at a local station exceeds that station's assigned burst duration so that some of the messages which are ready for transmission cannot be transmitted and may be frozen-out. To avoid or minimize the effects of message freeze-out, the various types of messages are categorized into a hierarchy of priorities for transmission.

Abstract: The invention finds application in a TDMA communications controller having a plurality of i input/output ports. The input/output ports transfer data from respective, local data users to a transmit bus and transfer data from a receive bus to respective local users on a time interleaved basis during periodic TDMA frames. Each port operates at its own data rate R.sub.i, with data ports having different data rates in the controller. The invention includes a test card which has a read-only memory (ROM) for storing test patterns for each of the data rates R.sub.i. The test card further includes a random access memory (RAM) having an input connected to the ROM, for storing one of the test patterns from the ROM. The test card further includes a processor having control outputs to the RAM and the ROM for controlling the transfer of one of the test patterns from the ROM to the RAM for the data rate R.sub.j of the data port under test.

Abstract: A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Abstract: A call processor is disclosed for a satellite communications controller, having a plurality of M voice ports, with an E lead input and an M lead output connected to each of a first subplurality of voice ports for rotary dial telephones, a tone digit interface connected to each of a second subplurality of voice ports which are dedicated to transducing a tone digit received from a multifrequency dialing telephone which is connected to one of a third plurality of voice ports. The third voice ports are connected by means of an intranodal wrap through a digital switch in the communications controller with the transducing circuits at the second voice ports so that the transducing circuitry can be shared among all of the third plurality of voice ports connected to multifrequency dialing telephones. The call processor employs a substantial amount of processing logic in the form of clocked control logic which is executed in a nested time slice operation.

Abstract: A double level metal interconnection structure and process for making same are disclosed, wherein an etch-stop layer is formed on the first metal layer to prevent over-etching thereof when forming the second level metal line in a via hole in an insulating layer thereover, by means of reactive plasma etching. The etch-stop layer is composed of chromium and the reactive plasma etching is carried out with a halocarbon gas.

Abstract: A time division multiple access satellite communication architecture is disclosed to achieve a relatively simple control procedure for permitting multiple computers to establish peer coupled transmission paths for high speed transfer by dynamically allocating satellite communication facilities in a sequentially shared broadcast mode. Each sequentially established CPU-to-CPU logical link takes the form of a point-to-multipoint sub-network which incorporates a standard data link control protocol for the control of information transfer. The function of the primary station is sequentially passed from station to station within the network and as each station assumes primary control of its logical point-to-multipoint circuit, other stations conform to the secondary role for that logical link configuration.

Abstract: A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L.sub.D to the drain. However, the introduction of the depletion extension L.sub.D introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length L.sub.D and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its L.sub.D relatively shorter, the companion device will also have its L.sub.D correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the L.sub.D for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective L.sub.

Abstract: For the multiplex transmission of coded speech signals in periodic frames, single segments (blocks of coded samples) are selectively suppressed for redundancy reduction, and are replaced on the receiver side by optimally correlated subsections of equal length from previously transmitted segments. On the transmitter side, a multiplicity of compare operations are made for each speech signal, between the respective newest coded segment and a step wise shifted subsection window of previous segments, to determine the best correlated subsection, i.e. the one which is most suitable as replacement and the respective relative offset and correlation. From a group of speech signals, the one signal, or several signals, having the best correlation is selected for suppression of a segment before transmission. Instead of each missing segment an indication of the corresponding optimum offset is transmitted in the frame header.