Abstract: A CMOS circuit is disclosed which has a latent image feature for application in FET memory arrays for writable read only storage applications. A four device cross-coupled CMOS circuit is formed with minimum real estate area, so as to allow for wiring level programming into a preconditioned binary one or zero state. The preconditioned circuit will assume a preselected binary state when power is turned on. Thereafter, the circuit can be accessed for normal binary one and zero selective storage without a significant diminution in its operating characteristics, when compared with conventional CMOS cross-coupled storage circuits.

Abstract: A photoresist photolithographic process is disclosed which provides for a single development step to develop a dual layer photoresist for lift-off, reactive ion etching, or ion implantation processes requiring a precise aperture size at the top of the photoresist layer.The process involves the deposition of two compositionally similar layers, with the first layer having the characteristic of being soluble in a developer after exposure to light and baking, and the second layer having the characteristic of being insoluble in the same developer after having been exposed to light and baked. With these two distinct characteristics for the two layers of photoresist, the effective aperture for windows in the composite photoresist can be tightly controlled in its cross-sectional dimension in the face of large variations in the developer concentration and development time.

Abstract: A method making self-aligned semiconductors utilizing two resist masking steps to form a device; making one of the masks insoluable with respect to the other so that when a first part of the device is formed by a first mask, and a second part of the device is formed by the second masks, the parts are self-aligned when the first resist is dissolved.

Abstract: An improved software cryptographic apparatus and method are disclosed. The apparatus and method enables the encryption of the object code of a program so as to enable relocatable code operations. The apparatus and method will adapt program execution for a mixture of encrypted and nonencrypted code. A particular advantage of the apparatus and method is its accommodation of interrupts and branches while carrying out the cryptographic function.

Abstract: A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders, to allow slower bits to skip past a stage while faster bits must go through that stage, thereby speeding up the multiplier's overall speed of operation. The complement carry technique minimizes hardware by allowing sums and carries to be generated by the carry save adders in either a true or a complement form. The skip technique takes advantage of the fact that the generation of a carry bit is faster than the generation of a sum bit. In the case of a four stage carry save adder designed for a multiplier, the skip technique reduces the number of circuit delays from the existing eight to the improved seven, without the addition of any hardware. Thus, the technique can result in a speed improvement for a multiplier.

Abstract: A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.

Abstract: A monitoring technique is disclosed for determining when the end point has been achieved in the evaporation of the constituents from an alloy such as a tin lead alloy. An optical pyrometer or other temperature sensing device, is focused on a crucible in which both tin and lead is being heated. Since, under vacuum conditions, lead evaporates at a lower boiling point than does tin, the temperature of the crucible will achieve a first temperature plateau while the lead is being evaporated. After the lead has been depleted in the crucible, the temperature of the crucible will rise to a higher temperature plateau at which the tin will evaporate. The output of the optical pyrometer is digitized and is applied to a microcomputer which periodically samples the temperature of the crucible.

Abstract: A system is disclosed to provide X.21 in-band call establishment signaling in the data path of a data communication system by utilizing a data port, digital switch and telephone signaling call processor in a satellite communications controller. The system includes an X.21 signaling protocol between a DTE and the satellite communications controller on the terrestrial side and allows self-switched digital data port functions in lieu of associated voice port and line functions as practiced in the prior art. An important aspect is that the signaling rate is the same as the line data rate. The data port goes through three generalized states during a normal call process. The first general state is idle, the second general state is the signaling state and the third general state is the data transfer state. At the start of the signaling state, the E input to the call processor is activated for the appropriate port. Call establishment signals are then processed through the digital switch and an X.

Abstract: A precision regulation substrate voltage generator circuit is disclosed which employs frequency modulation to modify the oscillator frequency driving the substrate charge pump, in order to more precisely control the resultant substrate voltage in an integrated circuit.

Abstract: The process sequence is disclosed which applies a polycrystalline silicon gate material, then applies a chemical vapor deposition oxide over all surfaces, forming an effective sidewall on each of the polycrystalline silicon gate structures. An ion implantation step is then carried out to implant source and drain regions whose proximate edges are not aligned with the edges of the polycrystalline silicon gate material itself, due to the masking effect of the sidewall portion of the chemical vapor deposition oxide layer. Thereafter, the chemical vapor deposition oxide sidewall material is selectively removed for those FET device locations where an active FET device is desired to be formed in the operation of personalizing the read only storage or PLA product. Those locations are then ion implanted for source and drain extensions which are then self-aligned with the respective edges of the respective polycrystalline silicon gate electrodes.

Abstract: A reactive ion etching technique is disclosed for etching a gate electrode out of layers of tungsten silicide and polycrystalline silicon without etching the underlying layer of silicon dioxide which serves as the gate dielectric and which covers the source and drain regions. The key feature of the invention, wherein the gate, which has been partially etched out of the tungsten silicide and polycrystalline silicon layers, is coated with poly tetra-fluoroethylene (teflon) to protect the sidewalls of the gate from being excessively etched in the lateral direction while the etching continues at the bottom on either side of the gate.The process is especially suitable for formation of tungsten silicide structures since no subsequent thermal steps are required which would otherwise cause a delamination of the tungsten silicide.

Abstract: A "natural" threshold device is serially connected between the gate of an output depletion mode FET device and the input node to an FET device so as to provide current flow from the input node to the gate of the FET device as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the depletion mode device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output load device, thereby providing a faster rise time for the output waveform.

Abstract: A bipolar transistor integrated circuit PLA is disclosed. The array includes a first and second mutually isolated epitaxial regions in a semiconductor substrate. A plurality of common collector bipolar transistors are formed in the first epitaxial region with selected ones of the plurality having their emitters connected in common to a first current source. A second plurality of common collector bipolar transistors in the second epitaxial region have the emitters of selected ones of the second plurality connected in common to the first epitaxial region. The bases of the corresponding pairs of transistors from the first and second epitaxial region are connected to an input signal source. The second epitaxial region is connected to an output node. In this manner, a cascode connected PLA is formed which eliminates the need for surplus current sources required in the prior art. The dot OR formed by the circuit effectively merges the prior art OR array with the search array.

Abstract: A method and apparatus are disclosed for conducting broadcast, multipoint, and conference communications in a TDMA network at various data rates while simultaneously conducting point-to-point communications at other data rates, either between local ports or between geographically remote ports during time intervals within a TDMA burst, which are not necessarily predefined. The disclosed apparatus appends a direct destination address to each point-to-point port communication for transmission over a communications link, to directly address the intended destination port. The disclosed invention appends an indirect destination address to each broadcast communication transmitted over the communications link. A broadcast memory is provided at the receiving end of the communications link, for storing correlated direct addresses which are accessed by the indirect destination addresses, to directly address a plurality of intended destination ports.

Abstract: Synchronization can be acquired between a transmitting node and a receiving node on a time division multiple access communication link without the necessity for additional data bits in the data stream, by correlating the number of errors detected in any interval as revealed by the forward error correction field. Both synchronization bits and stuffing bits can be located without using any external frame timing information. Substantial bandwidth savings is achieved by the technique, which can be applied for arbitrary combinations of the number of input ports, the number of data bits per group, and the number of parity bits generated per group.

Abstract: An interrupt processor is disclosed for an instruction pipelined digital processor, which includes an instruction classification system with a logic class decoder, a multistage, pipelined, interruptible-sequence detector, a multistage variable-return-address generator, and an active instruction completion, suppression, and termination control, to enable interrupting a sequence of instructions which execute out-of-order in the pipelined and digital processor, and to enable allowing a subsequent return to the interrupted program to resume processing of that program without error.

Abstract: Level sensitive scan design (LSSD) scan strings on an integrated digital logic circuit chip are employed for multiple functions of providing control parameters to logic blocks on the integrated circuit chip, and for providing reconfiguration messages to reconfiguration logic on the integrated circuit chip, in addition to the normal function of transferring test data to various portions of the integrated circuit chip. This reduces the number of input/output pads on the integrated circuit chip which must be dedicated to these functions.

Abstract: A combined read-only storage (ROS) and read/write random access memory (RAM) integrated circuit memory cell is disclosed. In a first cell embodiment, a ROS FET device and a RAM FET device are connected in common to a bit sensing line connected to a sense amplifier which senses if the ROS FET device has discharged the bit sensing line indicating that a gate is present on the ROS FET device. A write driver circuit is also connected to the bit sensing line, for providing current through the RAM FET device to the charge storage element for writing a one or a zero therein. In a second cell embodiment, a combined two-bit read-only storage and one-bit read/write random access memory integrated circuit cell is disclosed. The bit sensing line is shared by two ROS FET devices and one RAM FET device. In a third cell embodiment of the invention, a single binary bit is stored for read-only storage and a single binary bit is stored for read/write random access memory storage.

Abstract: A testing technique is disclosed for assuring AC performance of high speed random logic, employing a low speed tester. AC testing on a low speed tester is split into multiple phases. During the first phase, a slack time delta is introduced, which is the time difference between the product cycle time required by the application and the tester cycle time used in the product test. The product is tested with this timing using conventionally generated test patterns. The effect of the slack is then resolved in the subsequent phases of the test. The product is tested again with the same type test patterns as in the first phase, but with redefined strobe times at the staging latches in the circuit. The slack delta is transferred to paths between the consecutive staging latches and the resultant signals arrive and get sampled by the low speed tester as if there were no slack.

Abstract: An improved bistable FET circuit is disclosed which employs a reduced number of device elements and occupies less space in an integrated circuit. The flip-flop circuit includes the FET device having its source connected to a first potential and a second FET device having its source also connected to the first potential. The first FET device has a gate electrode composed of a resistive material with the first side connected to the drain of the second FET device and the second side connected to a second potential. The second FET device has a gate electrode comprised of a resistive material with the first side connected to the drain of the first FET device and a second side connected to the second potential. In this manner, the resistive gate of the first device serves as the load for the second device and the resistive gate of the second device serves as the load for the first device. Application of this circuit to electrically programmable PLA's and to random access memories is disclosed.