Abstract: An on chip monitoring circuit is disclosed which enables the rapid characterization of signal propagation speed for integrated circuits on the same chip. The circuit is based upon a correlation between signal propagation speed on the chip and the low pass filtering characteristics of the monitoring circuit, which is a classical first order low pass filter. The monitoring circuit performs the low pass filter operation from which the operator can determine what the signal propagation characteristics are for other integrated circuits on the chip resulting from specific process parameters which occurred during the fabrication of the chip. A feature of the invention is its ability to characterize very small capacitive and resistive contributions to signal propagation delay by using input driving frequencies which are moderately low, by using the principle of the Miller Theorem.

Abstract: A current pulse signal, which is generated by an optical detector, is fed to an input of an edge detector circuit. The current pulse signal is converted into a differentiated voltage pulse signal having a negative going pulse corresponding to a positive going slope of the input signal and a positive going pulse corresponding to the negative going slope of the input waveform. The positive differentiated pulse has a rise amplitude which is larger than its fall amplitude so that its most positive down level has a relatively positive absolute voltage value. Correspondingly, the negative differentiated pulse has a fall amplitude which is greater than its rising amplitude so that its most negative up level is more negative in absolute value than a nominal median zero voltage reference level.

Abstract: A combined finger touch and stylus detection system is disclosed for use on the viewing surface of the visual display device. Transparent conductors arranged in horizontal and vertical grid are supported on a flexible, transparent overlay membrane which is adaptable to a variety of displays. A unique interconnection pattern is provided between the transparent conductors in the array and buses which interconnect the conductors with the supporting electronics, whereby a minimum number of bus wires can be employed to service the array conductors and yet both unique finger touch location sensing and unique stylus location sensing can be accomplished. The system includes a control processor which operates on stored program instructions which, in a first embodiment provides for the alternate detection of either finger touch location or stylus location and, in a second embodiment, provides for the simultaneous detection of both finger touch location and stylus location.

Abstract: A call progress monitor for a computer telephone interface system. Energy detectors are connected to receive signals from a telephone line. A bandpass filter is connected to the telephone line, having selectable center frequency. A counter-timer connected to count clock pulses is reset by the energy detector and timing commences in response to the presence of a signal on the telephone line. The counter will result in a center frequency control means for the filter being slewed over a bandwidth of interest, in synchronism with the counting of the timer-counter. A signal detector connected to the filter indicates the presence of a pair of signal tones passing through the filter as it is slewed. Decoding means are connected to the counter-timer and the signal detector for generating a binary signal indicating the frequency of the bandpass filter which passes each signal tone. The binary signal is entered in a data register, and an interrupt posted to a host computer.

Abstract: A hierarchical complex logic tester architecture is disclosed which minimizes the encoding of program information for testing. The architecture takes advantage of the fact that much of the information applied as test signals to pins of a device under test, changes little from test cycle to test cycle. In one aspect of the invention, run length encoding techniques are used for identifying the number of test cycles over which a given test pin is to be maintained in a particular signal state. In another aspect of the invention, use is made of a small memory associated with each signal pin of the device to be tested. There may be a small plurality of for example, 16 different kinds of signals which can be applied to or received from a given signal pin of a device under test. The dedicated small memory associated with each device pin to be tested, will have the ability to store from one to 16 states.

Abstract: An apparatus for removing a mask which extends beyond the outer edges of a semiconductor wafer bonded thereto. The apparatus includes a base having a vacuum chamber opening onto the upper surface of the base, a vacuum valve separating the vacuum chamber from a vacuum source, an actuating lever and a mask discharge facilitator. The discharge facilitator comprising a horizontal plate having a plurality of vertical pins around the periphery thereof. When the lever is actuated, it opens the vacuum valve and lifts the discharge facilitator forcing the vertical pins into contact with the mask. The simultaneous application of the vacuum holding force, and vertical force applied by the pins causes the separation of the mask from the upper surface of the wafer.

Abstract: A fast writing circuit is disclosed for a soft error protected storage cell, such as a latch. The protected latch has a first input/output node and a second input/output node which are respectively connected to a charging source. The latch is connected to a first binary state input device which is enabled by a write-enable input, the first node being selectively charged during a write interval when the write-enable input is on, to represent a stored, first binary logic state for the latch. The soft error protection circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance when its gate is biased with respect to the diffusion electrode.

Abstract: An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-type translator having an input connected to receive the first operand, for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator having a first input connected to the output of the translator and a second input connected to receive the second operand, for multiplying the translated first operand times the second operand and outputting partial products consisting of signed digits. The multiplier further includes an array of adders, each adder having an input connected to two of the signed digits output from the partial product generator, for providing a sum consisting of a sequence of signed digits.

Abstract: A selective true or complement storage latch is disclosed which includes a data input switch having an input node connecting to a binary bit input source, a control input for accepting a first or second control state, a first data output node which is selectively connected to the data input node when the control input is in the first state and a second data output node which is selectively connected to the data input node when the control input is in the second state. There is also a first inverting gate having an input connected to the first data output of the data input switch and an output connected to a first storage node. The second inverting gate has an input connected to the first storage node and an output connected to the second storage node, the input of the second inverting gate being connected to the second output of the data input switch, the output of the second inverting gate being connected to the input of the first inverting gate.

Abstract: An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

Abstract: A universal calibration standard for surface inspection systems has a plurality of hemispherical pads which simulate the liquid scattering due to particulate contamination. The hemispherical pads scatter light irrespective of angles of illumination and detection and of rotational orientation, and are fabricated using ball-limiting metallurgical techniques. Any number and sizes of pads can be arranged on a substrate and the standard can be repeatedly cleaned, thereby having a long useful life.

Abstract: The disclosed circuit employs a single programmable timer and address decoder which identifies a plurality of bursts received from other stations in a TDMA communications network by means by identifying their origin addresses, and then starts associated timing intervals in the programmable timer for each burst. The instant when the intervals being timed terminate, corresponds approximately to the instant at which the local station should commence its transmission burst. The programmable timer and synchronizer associates each of a plurality of timing intervals with each of the plurality of transmitting stations in the TDMA network, and terminates each respective interval at approximately the same instant in a given local station, thus allowing the time for commencement of the local station's transmission burst to be reliably determined without regard for the participation of any more than one other of the plurality of transmitting stations in the TDMA network.

Abstract: A process is disclosed for simultaneously etching holes in both the thick and thin portions of a dielectric layer on a semiconductor substrate. An anisotropic dry etchant is used to eliminate any significant lateral etching of the dielectric layer during etching. Thus, a mask-and-etch cycle may be eliminated from processing during integrated circuit manufacture, yet dimensional tolerances are maintained.

Abstract: A soft error protection circuit is disclosed for a storage cell, such as a latch having a first input/output node and a second input/output node which are respectively connected to a charging source, the first node being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance. An inverter circuit has an input connected to the second node and an output connected to the gate electrode of the capacitor, for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node.

Abstract: A high speed, integrated circuit microprocessor includes a microinstruction sequencer for sequentially generating a plurality of N control words per period, each control word having a plurality of M bits. The microsequencer includes a storage register in the integrated circuit, having a plurality of M times N storage locations, for storing a microinstruction containing the N control words. The microsequencer also includes an N bit shift register in the integrated circuit, having N sequential outputs and a clock input with a cycle time equal to 1/N of the period, for propagating a binary bit therethrough to sequentially provide an enabling bit to each of the respective N outputs thereof. A plurality of M logic stages is also included in the integrated circuit, each stage including a plurality of two-input N AND gates. An i.sup.th one of these N AND gates in each stage has a first input connected to an i.sup.

Abstract: A DC power switching circuit connecting a load to a DC power source while suppressing arcing across a relay in the network. A normally open relay has its energizing coil connected to the control input of the circuit, the opposite end of the coil being connected to the gate of a silicon controlled rectifier. The SCR has its principal current conducting path connected between the load and the DC power source, for conducting current between the load and the power source during a first delay interval, thereby reducing the potential difference between the contacts of the relay so as to prevent its arcing during the closure of the contacts. An FET device has its principal current conducting path connected between the load and the DC power source and has its gate connected to a timer.

Abstract: A testing mechanism is disclosed for incorporation with the gripping fingers of a robot arm, to enable the real time testing of a device under test after it is picked up by the grippers. The robot arm has opposed fingers mounted thereon for transverse clamping of the sides of the device under test, which can be a semiconductor module. Mounted to the robot arm is a test head which can be brought into electrical contact with the pins of the device under test when the device has been picked up by the arm. Test signals supplied through the test head will conduct real time testing of the device while it is being transported by the robot arm from the pick-up point to one of several destination receptacles. The identity of the destination receptacle into which the tested device will be deposited, will depend upon the results of the real time test being carried out while the device is being transported.

Abstract: A mechanism is disclosed for a time division multiple access communications network, to enable the synchronizing of traffic messages between a transmitting and a receiving node. A transmit clock mechanism at the transmitting node includes a slip counter for accumulating a slip count value during consecutive intervals of transmission. The slip count value is transmitted along with the traffic messages over the communications link to the receiving node. A slip count detector is located at the receiving node, for receiving the slip count value and adjusting the receive clock at the receiving node in response to the slip count value. In this manner, a timing slip adjustment which has been made at the transmitting node will have a corresponding timing slip adjustment imposed at the receiving node so as to maintain the proper synchronization between the sending and receiving stations during a time division multiple access communications session.

Abstract: A substrate voltage generator is disclosed which provides over 1.5 times as much current for a given size circuit, as has been capable with prior art substrate voltage generators. This is achieved by means of a high capacitance per unit area charge pumping capacitor having a triple plate structure and further through the space saving technique of providing a dual use for the source diffusion of the current sinking device in the circuit so as to also serve as the guard ring around the charge pumping circuit of the substrate voltage generator. These and other features of the substrate voltage generator circuit enable relatively large quantities of current to be supplied for maintaining the substrate voltage in large dimension VLSI chips having significant diffusion leakage currents.

Abstract: A quaternary FET read only memory is disclosed wherein each FET storage element in the array has its threshold adjusted by ion-implantation to one of four values. Each FET element in the array has its drain connected to a drain potential V.sub.DD. A binary input signal from a conventional binary, true/complement generator will then enable the gate of a selected FET storage cell and the output potential at the source of that selected storage cell will be V.sub.DD minus the customized threshold voltage of that storage cell, which is output at an output node. The signal on the output node is a quaternary signal which may be amplified by a quaternary sense amplifier circuit and then converted from quaternary to binary signal by means of a converter. The quaternary read only memory is capable of storing twice as much information per unit area as is a conventional FET binary read only memory. The concept may be expanded to N levels of information storage, using FET array devices with N different threshold voltages.