Abstract: A signal generator responsive to a normal mode signal by generating control signals for displaying low luminance foreground pixels and high luminance background pixels. In addition, the signal generator is responsive to a high intensity mode signal by generating control signals for displaying zero luminance foreground pixels and high luminance background pixels.

Abstract: An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler.

Abstract: A method and system for allowing multiple tasks to share virtual memory areas, in a memory management system for a computer, uses a data structure which maintains a list of address spaces shared by more than one task. For each entry in this list, a list of slots in virtual address space is maintained in the data structure, where each slot contains indications that said shared memory was mapped into a task. An offset table of directory pages is also maintained, and each entry in this directory points to a directory page for a task. The directory page entries for all of such directory pages points to a page table entry. An entry in each of the offset tables points to the entry in the list of shared address spaces for this set.

Abstract: In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in parallel instead of sequentially, the critical path through a multiple way set associative instruction cache is through a directory and compare circuit which selects which way instructions will be retrieved. This patch is known as the late select path. A multi-ported effective address (EA) directory is provided and is accessed prior to selection of a fetch address which fetches the next set of instructions from the cache. In this manner, the time required for the late select path can be reduced.

Abstract: An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel extension which is more application-level than kernel level. The implementation-independent kernel is involved only at very minimum level for a prologue to the exception handling routine. First, a kernel extension registers an exception with the processor by storing the address of a pointer to a first-level interrupt handler; this address is stored in a location in kernel data storage, in non-paged memory. When an exception condition is reached, state is saved and the address location is checked to see if an exception has been registered. If so, the address is used to go to the first-level interrupt handler, which is at the kernel extension level. The first-level interrupt handler may access a second-level interrupt handler.

Abstract: An improved method and apparatus in pen-based computer systems using a tablet input device to select the outer boundary area of a graphics display through use of a virtual cursory boundary is disclosed. The tablet input device has a first inner active area surrounded by a second outer active boundary. An operator selectively moving a pointing device in the first inner active area of the tablet input device causes a cursor to move correspondingly on the graphics display image. When the operator selectively moves the pointing device in the second outer active area, the digitizing table causes the cursor to move to a corresponding graphics display boundary position.

Abstract: A system for routing an "object" (in the sense that object means an abstraction that encapsulates data in a known way, with a known list of operations or methods to access the data, and the object has a unique identity, is mobile, and possibly persistent). The "object" is routed in a distributed computing system along an action path (itself an "object") which defines the logical path to be traversed by the object. The action path consists of action stops naming or describing functionally principals (people or automated mechanisms) required to act upon the routed object in a prescribed order. The object routing system propagates the object along this action path, and monitors and controls its progress until it completes the path. The system includes mechanisms of dispatching the routed object between principals, finding the principals required to act on the routed object, notifying the principals in turn of their required action, and potentially relocating the routed object to the nodes of the principals.

Abstract: A computer system allows for a hardware structure to participate in the transmission of P1394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features.

Abstract: An apparatus for managing operations of a circuit, including apparatus for computing a cumulative thermal load caused by instructions to be executed by the circuit, apparatus for determining whether the cumulative thermal load exceeds a thermal range of the circuit, and apparatus, coupled to the apparatus for determining, for reducing the cumulative thermal load of the circuit prior to execution of the instructions determined to cause the thermal range to be exceeded. In addition, a method for managing operations of a circuit, including the steps of computing a cumulative thermal load caused by instructions to be executed by the circuit, determining whether the cumulative thermal load exceeds a thermal range of the circuit, and reducing, subsequent to the step of determining, the cumulative thermal load of the circuit prior to execution of the instructions determined to cause the thermal range to be exceeded.

Abstract: To rapidly draw straight lines and circular arcs of width 1 on a raster scan graphic display by determining whether or not the point, the X coordinate of which is incremented by 1 relative to the current point, and the point, the Y coordinate of which is incremented by 1 relative to the current point, are between the outlines f1 and f2 defining a straight line of width 1. If the point, the x coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next pixel. If this is not the case, and the point, the y coordinate of which is incremented by 1, is between the outlines f1 and f2, it is plotted and selected as the next point. If neither point is between the outlines f1 and f2, the point, the x and y coordinates of which are incremented by 1, is plotted and selected as the next pixel.

Abstract: A phase shifting method uses a special interferometer in which the illuminating beam is divided into two or more components and the mask is irradiated from both sides. The pattern to be transferred onto the wafer (the mask) is generated on an optically transmissive substrate by appropriately combining reflective, transparent and absorptive areas. The optical paths of the beams illuminating the back side and the front side of the mask (that will be called transmitted and reflected beams respectively) are chosen so that the phase of the two beams is different by approximately an odd multiple of .pi. radians at the surface of the mask. The combined beams are projected onto the target wafer by suitable optics. The phase difference between the illuminating beams reduces the edge blurring that results from diffraction effects.

Abstract: A random-access type storage device such as a hard disk or semiconductor memory is formatted to provide multiple partitions of varying block size. The data to be stored is in blocks of fixed size, and these blocks are compressed if the compressed size fits in the block size of a small-block partition in the storage device. If a data block is not compressible to the small block size, it is stored uncompressed in another of the partitions. The memory device also contains a table storing the locations of the blocks in the partitions, so upon recall the block is retrieved from location, decompressed (if it had been compressed), and sent to the CPU. For example, there may be two partitions, one using the block size of the original (uncompressed) data, and the other having a block size corresponding to the typical compressed size of the blocks of data (perhaps one-half the size of the original data blocks). The relative number of blocks in each partition (e.g.

Abstract: A method for making semiconductor devices such as dynamic read/write memory cell arrays of the one-transistor N- channel silicon gate type employs an ion implant of high dosage to produce N+ source/drain regions. The transistor and capacitor gates are in place when this implant is performed, and the chain oxide beneath the gates can break down due to static charge produced on the slice surface as a result of the ion implant. To prevent build-up of static charge on the surface, a thin coating of polysilicon is applied before the implant and grounded. This coating is subsequently removed by thermal oxidation or etching. Alternatively, a thermal oxide coating may be used as it will prevent the implanted arsenic from reaching the polysilicon gates, although it will penetrate a thinner thermal oxide coating over the source/drain area. Other dielectric films such as silicon nitride may also be used.

Abstract: A synchronous rectifier power supply circuit has a pair of power MOS transistors connected in series with the primary and secondary of a transformer, respectively, and another power MOS transistor connected across an inductive load on the secondary side. The gates of the pair of transistors are driven by a pulse source which is pulse-width modulated in response to the load voltage, and the other transistor has its gate driven by the inverse of the pulse source. To prevent current spikes and power losses due to the pair of transistors being on during a transition period at the same time the other transistor is on, a high-gain bistable logic circuit is used to drive the gates; A NOR gate prevent the gate of the other transistor from rising to a turn-on voltage until the gates of the pair of transistors are at below a turn-on voltage. A second NOR gate prevents the gates of the pair of transistors from reaching a turn-on voltage until the gate of the other transistor is below a turn-on voltage.

Abstract: A process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.

Abstract: A memory array having two separate sets of parallel bit lines, and a word line intersecting the sets of bit lines. The memory cells are floating-gate MOS transistors having gates coupled to associated ones of the word lines and source-to-drain paths connected between alternating ones of the sets of bit lines and ground lines.

Abstract: A discharge circuit for discharging bit lines of an array of semiconductor memory cells in which the array of bit lines are biased from a single bias line. The discharge circuit includes a discharge switch coupled to the bias line for discharging the bit lines and the bias line and a control circuit coupled to the discharge switch operative to turn on the discharge switch in response to the voltage on the bias line rising above a first predetermined level and then to turn off the discharge switch in response to the voltage on the bias line falling below a second predetermined level.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all macrocode bits is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to address all bytes of macrocode and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.

Abstract: An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.

Abstract: A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to said Y address decoder. Switch means isolates either the first or second set of input/output lines from the Y decoder. A programmable non-volatile memory element is coupled to programming ones of the input lines and is programmable into a programmed state from an unprogrammed state in response to a programming voltage applied to programming ones of the first set of input lines. A control circuit is coupled to the switch means and to the memory element for isolating the first or second set in response to an external signal applied to a selecting one of the first set of input/output lines and in response to the state of the non-volatile memory element.