Abstract: An array of programmable memory cells having spaced apart bit lines, spaced conducting word lines crossing over the bit lines and electrically conductive lead lines crossing over the word line which includes electrically conductive contacts between lead lines and corresponding bit lines. Each contact is located at an opposite side of a selected number of word lines to contacts between adjacent lead lines and associated bit lines so that when viewed in plan the contacts are staggered from one lead line to the next.

Abstract: A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

Abstract: A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. A thin layer of titanium or the like is deposited, extending into a contact hole, then polysilicon is deposited over the titanium coating the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create a titanium silicide layer, including conductive sidewalls or a plug. Metal contacts and interconnections then engage the direct-reacted silicide rather than relying upon step coverage.

Abstract: An electrically programmable read only memory device formed in a face of a semiconductor substrate of a first conductivity type which includes a pair of spaced apart thick oxide isolation regions defining an elongated channel of the substrate therebetween. A floating gate of conductive material overlies a portion of one of the isolation regions and a first portion of the elongated channel being separated from the oxide isolation and channel regions by an insulator layer. A control layer of conductive material extends over the channel and the floating gate separated from both of the latter by an insulator layer. Buried diffused regions are located below each oxide isolation region.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22). The surface of oxide layer (22) is nonuniformly substantially roughened. A layer of metal (24) such as aluminum is formed over the oxide layer (22) and extends into the aperture (32) for contact with a portion of the device (10). The layer of metal (24) has increased granular structure and a roughened exterior surface to provide enhanced electromigration properties.

Abstract: Erasable programmable memory cell having a control gate, a row line and bit line is disclosed. Line driving circuitry coupled to the bit line and control gate applies a negative voltage to the bit line during the ERASE mode. The latter voltage is such that the voltage across the control gate, floating gate and drain of the floating gate transistor is sufficiently great to cause charging of the floating gate. The construction of the line driving circuit for applying the various voltages, including the negative erase voltage, to the control gate of the floating gate transistor is also disclosed. The line driving circuit is responsive to a control signal indicating the operating mode of the memory, and further includes blocking transistors so that the V.sub.pp voltage of the write operation is not coupled back to the circuit input which receives the control signal.

Abstract: A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate.

Abstract: A simplified process for metal gate and contact/interconnect system for MOS VLSI devices employs a refractory metal structure for the gate, including a thick layer of tungsten alone, with stress and adhesion controlled by the deposition conditions. The metal gate receives sidewall oxide spacers during a metal-cladding operation for the source/drain areas. Contacts to the source/drain region include a molybdenum/tungsten stack and a top layer of gold.

Abstract: An array of electrically programmable semiconductor memory cells of a type having electrically conducting odd and even row lines, left and right column and ground lines and field oxide regions separating adjacent left and right cells. The array has a field plate over the field oxide region which extends underneath both odd and even row lines. A driver is coupled to the odd and even row lines in order to drive one of them to substantially ground potential while the other is driven high to a cell selection voltage.

Abstract: A data processing system which has an interface circuit that interfaces the data processing system to input devices. The interface includes an input means such as a pad for conducting signal levels from the interface devices to the data processing system. A digitizer, such as a Schmitt trigger, digitizes the signal levels to signal levels that are acceptable by the data processing system. An output line conditioner conditions the data lines that are connected to the digitizers to prevent overdriving of the data lines by the digitizers. Line drivers are used for driving the digitized system on the data lines throughout the data processing system.

Abstract: A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another.

Abstract: A device for changing the organization of an array of memory cells formed on a semiconductor ship using external control signals which includes a storage device for storing an external enable/disable command signal on the chip, a divider for dividing the array into blocks of memory cells in response to a stored enable command and a pass gate assembly for permitting access to selected ones of the blocks in response to corresponding toggle input signals when an enable command is stored.

Abstract: An integrated circuit oscillator which includes a capacitor, a reference current source coupled to the capacitor used to charge the latter, and a trigger circuit coupled to the capacitor having an upper input threshold for changing from a first state to a second state and a lower input threshold for changing from the second to the first state. A discharge circuit is coupled to the trigger circuit and is operative to discharge the capacitor in response to the trigger circuit changing states and to cease the discharging on changing back to its original state.

Abstract: A video display system employs a memory arrangement for the video data which is sequentially accessed for serial read-out of the bit-mapped video information at a high clock rate, and also randomly accessed in parallel by a microcomputer for generating and updating the information to be displayed. Parallel access to the memory by the microcomputer can occur while the serial video data is being clocked out, so microcomputer I/O and video output conflict only a very minimum amount. Dynamic MOS RAMs with a serial register added provide this dual port memory.

Abstract: An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transistor and a ground select transistor coupled to each of the drain and source lines. Each selected floating gate transistor in a programming mode is in series with control and ground select transistors between a high voltage Vpp and ground potential. A resistive element in series with a first conducting circuit element establishes a reference current which generates a voltage V.sub.1 at the junction of the resistive element and the circuit element. In a second current leg a second conducting circuit element, a module floating gate transistor biased into a conducting state and a module control transistor are all connected between Vpp and ground such that a voltage V.sub.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench; a partial etch followed by regrowth of oxide is used prior to the final etch for most of the depth of the trench, to thereby reduce the effect of undercut. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

Abstract: An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.