Patents Represented by Attorney, Agent or Law Firm Jones Volentine, LLP
  • Patent number: 6169027
    Abstract: The invention consists in a method of filling recesses in a surface layer of a workpiece with conductive material including the steps of: forming a barrier layer on the surface; depositing a layer of conductive material on to the barrier layer; and forcing, flowing or drifting the conductive material into the recesses characterized in that the barrier layer includes Oxygen or is oxidized and oxidized material in the surface of the layer is nitrided prior to the deposition of the conductive material.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: January 2, 2001
    Assignee: Trikon Equipments Limited
    Inventor: Christopher David Dobson
  • Patent number: 6166442
    Abstract: A semiconductor device is comprised of a first wire that has a plurality of via holes formed in the vicinity of an end thereof and that is connected to a conductor of a different layer through the via holes, and a plurality of slits that are provided parallel to the direction in which the first wire extends and that split the first wire into a plurality of second wires over a predetermined distance from the end thereof.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: December 26, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Makiko Nakamura
  • Patent number: 6158183
    Abstract: A panel for a padded enclosure, such as a large animal treatment room in veterinary practices, has a resilient body with an impermeable skin or a plastics coating (5) over one face (1) and the edges (2). The edges have longitudinal grooves (4) and the coating follows them so that when two panels are placed edge to edge there is a concealed void. These edges (2) are adhered and sealed together when lining the enclosure, coated faces innermost, but the sealant/adhesive (6) does not fill the voids. These voids compensate for the stiffness that would be inherent in a plain coated edge and make the cushioning effect of the padding substantially uniform.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: December 12, 2000
    Inventor: Thomas Bartlett Snell
  • Patent number: 6149507
    Abstract: A polishing method and apparatus for a semiconductor wafer includes a loading section having a loading platform for mounting a loading cassette, and a loading robot arm for transferring a wafer from the loading cassette. The apparatus includes a standby stage having a pre-polishing stand on which the wafer is placed, and a post-polishing stand for holding the wafer after polishing, and a polishing table on which a polishing process is performed. A wafer moving device transfers the wafer from the pre-polishing stand to the polishing table and back to the post-polishing stand. An unloading section includes an unloading platform for mounting an unloading cassette, and an unloading robot arm for transferring the wafer to the unloading cassette. A measurement device, proximal to the unloading stage, analyzes a polishing state of the wafer and then a cleaning device cleans the wafer after the wafers are analyzed.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: November 21, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-seon Lee, Jeong-kon Kim
  • Patent number: 6145900
    Abstract: A tweezer for adsorbing a semiconductor device allows easy and safe handling of the wafer by preventing rotation of the tweezer due to the weight of a wafer adsorbed off-center, and the breakage of the wafer caused thereby. The tweezer has a gun-shaped body, including a handle having a first vacuum line, and a barrel connected to the handle, the first vacuum line extending through the barrel. The first vacuum line is opened and closed by a trigger and shutter. A head is non-rotatably attached to the barrel, the head having a second vacuum line connected to the first vacuum line for adsorbing the wafer by the vacuum supplied inside the second vacuum line.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: November 14, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yui-kun Jung
  • Patent number: 6137318
    Abstract: A constantly conductive MOS transistor is placed in a logic circuit including a plurality of switching MOS transistors. The switching MOS transistors and the constantly conductive MOS transistor are connected in series and each receive a control signal at their respective gates. The constantly conductive transistor is in a conductive state regardless of the state of its control signal. Thus, it is difficult for a third party to learn the true logic structure of the logic circuit by visual inspection, as the third party will tend to recognize the constantly conductive transistor as a true transistor contributing to the logic circuit, and not as a constantly conductive "dummy" transistor.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: October 24, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kodama Takaaki
  • Patent number: 6133148
    Abstract: A method of depositing a thin film for a semiconductor device using a lamp heating type apparatus. In the method, a wafer is loaded into a processing chamber of the apparatus, and the pressure of the chamber and the temperature of a susceptor installed in the chamber are increased to a level higher than a deposition pressure and a deposition temperature, respectively. Then, the pressure of the chamber and the temperature of the susceptor are decreased to the deposition pressure and the deposition temperature, respectively, and a film is deposited on the wafer. The vacuum of the chamber is then released and the gas remaining in the chamber and a source gas injection tube is purged.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: October 17, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Kyoung-hoon Kim, Young-wook Park, Kab-jin Nam, Duk-soo Yoon, Sun-woo Kwak
  • Patent number: 6124623
    Abstract: An object of the present invention is to manufacture a semiconductor device excellent in withstand-voltage property of each element formed in a peripheral element region portion, without incurring complexity of a manufacturing process.Impurity ions are injected into a substrate so as to form a first well portion and field oxide films for partitioning a substrate surface including the surface of the first well portion into a plurality of active regions. Further, the impurity ions are injected into the first well portion so as to form a second well portion having a plurality of active regions. Regions corresponding to the active regions on the second well portion are exposed and a mask for covering regions other than the above regions is formed. Ions are injected into the second well portion exposed from the mask under the action of energy transmitted through the field oxide films.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: September 26, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yutaka Kamata
  • Patent number: 6119245
    Abstract: The aim is to improve reliability and life of a semiconductor storage device using memory elements for which deterioration is a problem. In a semiconductor disk device equipped with a flash memory section 110 having memory elements M(0).about.M(9) having a plurality of sectors used as ordinary sectors or spare sectors, and a disk controller section 120 that performs data writing/reading in respect of memory elements M(0).about.M(9) in accordance with address information input from outside, there are provided a data error information management table 127 that stores for each memory element the situation regarding occurrence of write/read error of memory elements M(0).about.M(9), a micro CPU 131 that detects deterioration of memory elements in accordance with the situation regarding occurrence of write/read error stored in data error information management table 127, and an address conversion table 128 that effects conversion of address information such that memory elements M(0).about.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: September 12, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shinji Hiratsuka
  • Patent number: 6118328
    Abstract: The invention intends to provide a semiconductor integrated circuit including MOS transistors, which is able to operate at a high-speed with a low power supply voltage in the active mode, and to reduce the power consumption resulting from the leakage current in the standby mode.In view of the foregoing object, the semiconductor integrated circuit of the invention is comprised of a first power supply line to which a first power supply potential is supplied, a virtual power supply line, a logic circuit connected to the virtual power supply line, a power control transistor provided between the first power supply line and the virtual power supply line, having a control electrode to which a first control signal is inputted, a second power supply line to which a second power supply potential is supplied, and a substrate potential control circuit connected to a substrate on which the power control transistor is formed, the first power supply line, and the second power supply line.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: September 12, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koichi Morikawa
  • Patent number: 6113754
    Abstract: A sputtering apparatus for manufacturing semiconductor devices, and a sputtering method using the same, allows for the formation of metal layers having good step coverage and good deposition rate. The sputtering apparatus for manufacturing semiconductor devices includes a process chamber; a target; a backing plate for the target; a cooling gas line on or in the backing plate, such that a cooling gas for cooling the target is circulated through the cooling gas line; and a cooling gas supply apparatus for supplying, discharging and recirculating cooling gas to and from the cooling gas line of the backing plate. The sputtering process is carried out with a high frequency power applied at 15 kW to 45 kW, argon gas supplied at 3 sccm to 10 sccm, and inner pressure in the process chamber at 0.1 mTorr to 1 mTorr. This sputtering apparatus does not require a collimator, therefore none of the particles generated when using a collimator are present to damage the wafers processed in this apparatus.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-suk Oh, Yoon-sei Park, Gyu-hwan Kwag
  • Patent number: 6113700
    Abstract: A gas diffuser for semiconductor device fabrication has the form of a hermetic cylinder with a hollow formed therein and is provided with a gas inlet opened upward for the gas to flow into the hollow, and a disk-shaped diffusion plate disposed in the lower side thereof with a plurality of nozzles to direct and control the stream of the gas pouring out of the hollow. The thickness of the diffusion plate increases with radial distance from the center thereof, such that lengths of the nozzles through which the gas passes also increase with radial distance from the center of the diffusion plate. A reaction furnace has the gas diffuser disposed in an upper portion thereof, and a support plate for supporting the wafer disposed in a lower portion thereof. The distance from the surface of the wafer to the diffusion plate of the gas diffuser is half the radius of the wafer.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-young Choi
  • Patent number: 6113734
    Abstract: An apparatus for opening/closing a process chamber door of an oven for manufacturing a semiconductor device includes a boss formed at one side of an opening of the process chamber, a shaft which passes freely through the center of the boss, bearings attached to the process chamber and rotatably supporting the ends of the shaft, a driver for rotating the shaft in opposite directions over a predetermined angle, and a door that seals the opening, one side of the door being attached to the shaft so as to be moved when the shaft rotates. Alternatively, the present invention provides a pair of bearings disposed beside one side of an opening of the process chamber, a shaft whose ends are rotatably supported by the bearings, a bracket having one end fixed to the shaft, and another end fixed to the door. A driver also rotates the shaft over a predetermined angle that opens and closes the door.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-young Woo, Woo-yeul Choi
  • Patent number: 6115297
    Abstract: A semiconductor memory circuit includes a memory cell subarray, a subarray driver and a cell drain potential generator. The memory cell subarray includes word lines, memory cell transistors and a cell drain line selection transistor. Each of the memory cell transistors has a gate connected to one of the word lines, a drain and a source. The cell drain line selection transistor has a first terminal connected to the drains of the memory cell transistors, a second terminal and a gate. The semiconductor memory circuit further has a subarray driver connected to the gate of the cell drain line selection transistor for applying a predetermined potential to the cell drain line selection transistor in response to a write control signal and an address signal, and a cell drain potential generator connected to the second terminal of the cell drain line selection transistor for providing a cell drain potential to the second terminal of the cell drain line selection transistor in response to the write control signal.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: September 5, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masahiko Nagatomo
  • Patent number: 6114237
    Abstract: A method of forming contacts of a semiconductor device while improving a step coverage and increasing margins between the device and an adjacent device. The novel method comprises the steps of forming an interlayer insulating film. A contact hole is formed in the interlayer insulating film. A mask layer is deposited over the contact hole to a thickness sufficient to withstand the planarization process and is planarization-etched. Wet-etching is performed over the entire semiconductor substrate, thereby etching the interlayer insulating film, wherein the wet-etching is characterized in that exposed portions of the interlayer insulating film outside of the contact hole and interfacing the mask layer are etched faster than other upper exposed portions of the interlayer insulating film. As a result, the contact hole has a sloped-sidewalls profile.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: No-Hyun Huh
  • Patent number: 6113697
    Abstract: In a photoresist coating apparatus and method, a rotating wafer is scanned with a spray nozzle from which the photoresist issues. The rotational speed of the wafer is varied based on the relative position of the nozzle above the wafer. The varying of the rotational speed is designed to minimize the amount of photoresist necessary for coating the wafer. Specifically, the photoresist is sprayed from the nozzle while the nozzle scans the wafer in a direction from the peripheral edge of the wafer toward its center, and the rotational speed of the wafer is increased during such scanning.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-woo Kim, Byung-joo Youn
  • Patent number: 6112430
    Abstract: A vacuum dryer and a method of drying a semiconductor device using the same are provided. In the present invention, a vacuum dryer using isopropyl alcohol vapor, including an outer bath, an inner bath, a main water supply line, a supplementary water supply line, an inner bath drain line, and an outer bath drain line, is provided. After cleaning the inside of the vacuum dryer, the inner bath is filled with the supplied deionized water and the deionized water is continuously overflowed. Then, the semiconductor substrate is loaded into the inner bath of the vacuum dryer to which the deionized is continuously overflowed. The loaded semiconductor substrate is dried by supplying the isopropyl alcohol vapor to the inner bath into which the semiconductor substrate is loaded.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 5, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-geun Park, Jong-jae Lee
  • Patent number: 6111815
    Abstract: A synchronous semiconductor burst nonvolatile semiconductor memory includes first and second address counter circuits and a counter selection circuit in order to output an address signal to a first latch circuit for storing therein data from a memory cell. Either the first address counter circuit or the second address counter circuit is alternately selected by the counter selection circuit in response to a burst control signal. According to the invention, either the first address counter circuit or the second address counter circuit is always selected, and a burst address signal is outputted to the latch circuit on the basis of an externally supplied address signal (first signal of the burst address signal) before the burst control signal is generated.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: August 29, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Keiichiro Takeda
  • Patent number: 6111637
    Abstract: A method and an apparatus for examining wafers includes a wafer cassette having a capacity for holding a plurality of wafers located on each of first and second locaters. The wafer cassettes are fixedly held on the first and second locaters during the wafer examination. A first indicator shows that the wafer cassettes are fixedly held on the first and second locaters. A robot arm sequentially carries each of the wafers between the first locator, an aligner, a scanning chamber and the second locater to examine the wafers. The wafer cassettes are released when the examination is complete, and a second indicator shows that the examination is complete.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: August 29, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Lee, Sang-Kyu Hahm, Young-Kyu Lim, Byoung-Seol Ahn
  • Patent number: 6112070
    Abstract: A receiving wave containing a desired signal and received through an antenna is inputted to an interstage band-pass filter 4 after the component outside a receiving band of the receiving wave has been attenuated by a receiving band-pass filter 2a. A phase locked loop circuit 9 outputs a frequency control voltage corresponding to a selected channel to a voltage control oscillator 8 and also outputs this frequency control voltage to an interstage band-pass filter 4 as a band control voltage thereof. The voltage control oscillator 8 generates a local carrier wave in response to the frequency control voltage. The interstage variable band-pass filter 4 has a passing band width which is a little wider than channel band width and varies its passing band in response to the band control voltage so as to include the selected channel, thereby attenuating the component outside the passing band of the receiving wave inputted from the low noise amplifier 3 and then inputs the receiving wave to a mixer 5.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: August 29, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tsutomu Katsuyama, Hiroshi Andou