Abstract: An apparatus for manufacturing a semiconductor device employs a vacuum system, in which a heating source is installed in a predetermined portion of a venting-gas inlet. A venting-speed controlling valve is installed in a predetermined portion of an exhaust pipe, for controlling the speed of gas flowing from a load lock chamber to a pump by controlling the opening and closing thereof. An exhaust pipe may have a main pipe with different diameters in different portions to reduce the venting speed. Accordingly, condensation-induced particle formation can be reduced by thus preventing adiabatic expansion of the gas in a load lock chamber.

Abstract: Test data TD, which are provided to a flipflop 11 of a scan flipflop 10-1 through a scan path 1S are latched with the timing of a clock signal CK that has been inverted at an inverter 12. An output signal S11 from the flipflop 11 is provided to a flipflop 14 via a selector 13, is latched at the flipflop 14 with the timing of the clock signal CK and is provided to a scan flipflop 10-2at the succeeding stage through a scan path 3S. In this manner, since the timing with which the test data TD change and the timing with which the clock signal CK rises are offset by 1/2 of the clock cycle, a reliable scanning operation is achieved regardless of the length of the paths such as the scan path 1S and the like.

Abstract: There is provided a semiconductor memory device 100 comprising memory cell blocks 20-1 to 20-n, decoder circuits 10-1 to 10-n that carry out the redundant operation provided so as to correspond to each memory cell block, a Roll Call signal transmission circuit 110 which detect if the redundant function is in operation; wherein each decoder circuit outputs a decoder signal FCi at low level to the Roll Call signal transmission circuit when the redundant function is in operation, but outputs a decoder signal at high level when the redundant function is not in operation, and wherein the Roll Call signal transmission circuit outputs a judgment signal at high level when all the decoder signals are at high level, but outputs a low level judgment signal when any of the decoder signals is at low level.

Abstract: With a VCO 1 which constitutes the voltage controlled oscillator according to the present invention, since NMOS transistors N11, N12 and N13 are provided in each of inverter circuits 11, 12 and 13, the oscillating frequency band can be divided into three sub ranges. As a result, even when the VCO gain effected by a control signal VCN is reduced, a wide frequency band is assured, thereby making it possible to easily support the clock frequency required by the system into which the VCO 1 is to be incorporated.

Abstract: Digital image data are input to a graphic memory circuit (G), and digital data stored in said graphic memory circuit (G) are read out using a control circuit (H). The graphic memory (G) has a control signal generator (N) for outputting a control signal (WAIT) during a read transfer or a write transfer, and an general purpose memory interface for receiving control signals (e) of a general purpose semiconductor memory. When the control circuit (H) is not outputting the control signal (WAIT), accesses to the graphic memory (G) are executed using general purpose memory control signals (e).

Abstract: An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.

Abstract: A test system for detecting integrated circuit (IC) devices having a short life time. The test system thermally, electrically and functionally tests the IC devices. The test system includes a selection signal generator with a memory device for writing external data into memory cells indicated by address signals and for reading the written external data as device selection signals. A counter sequentially increases the address signals entering into the memory device. The device selection signal patterns can be adjusted according to standard memory test patterns or user defined test patterns.

Abstract: A measurement system for a semiconductor manufacturing line for measuring at least one wafer, which has gone through a specified manufacturing process includes a plurality of checking parts and a robot for conveying the wafer between the checking parts. After being loaded by the robot, the wafer goes through each checking part, and is then unloaded. The measurement apparatus is connected to a control part which is interfaced with each checking part so that when the measurement of the wafer is completed at a certain checking part, the wafer is conveyed to another checking part and to the unloading portion.

Abstract: An operating system to be cooled is formed as a non-flow system so that the system can be protected from contaminants which could otherwise enter the system. When the temperature in the system is above a certain level, heat in the system is absorbed by a Peltier module utilizing a Peltier effect. A convection fan forces the air that is cooled by the Peltier module throughout the system.

Abstract: A semiconductor memory circuit comprises a plurality of redundancy address setting circuits and a decode circuit. Each of the redundancy address setting circuits has a first fuse coupled between a first voltage potential node and a first node, a second fuse coupled between the first node and a second node and a transistor coupled between the second node and a second voltage potential node. The decode circuit is coupled to the first nodes of each individual redundancy address setting circuits, for decoding signals which are applied to the first node and outputting a redundancy address signal according to the state of the first and second fuses.

Abstract: The present invention provides a semiconductor integrated circuit that solves the aforementioned problems. A semiconductor integrated circuit of the present invention has a plurality of memory cells, for respectively storing data, bit line pairs supplied with data read from the memory cells and sense amplifiers for amplifying data supplied to the bit line pairs. The integrated circuit also has first and second data bus driving transistors, and a pair of data buses. The first data bus driver transistors each have a control terminal, for receiving data supplied to one bit line of the bit line pairs, a second terminal connected to a common node, and a third terminal, while the second data bus driver transistors each have a control terminal, for receiving data supplied to the other bit line of the bit line pairs, one terminal connected to the common node, and a third terminal.

Abstract: An output circuit includes a first, second and third field effect transistors each having a channel of a first conductivity type. The first field effect transistor includes a gate connected to a first node, a first electrode connected to a first power supply and a second electrode connected to a second node. The second field effect transistor includes a gate connected to a third node, a first electrode connected to the second node, a second electrode connected to a fourth node and a substrate connected to a fifth node. The third field effect transistor includes a gate connected to a sixth node, a first electrode connected to the third node, a second electrode connected to the fourth node and a substrate connected to the fifth node. The output circuit further includes an inverter and a fourth field effect transistor having a channel of a second conductivity type which is opposite the first conductivity type.

Abstract: A lead frame transfer device includes a platform, and front and rear fingers for moving the lead frame from a transfer position to a feeding position, via the platform, with minimal impact and while producing minimal mechanical abrasion. Each of the fingers includes a plate-like support for the lead frame, a vertical cylinder for moving the support in a vertical direction, and a horizontal cylinder for moving the support in a horizontal direction. The device also has a sensor for detecting the presence of a lead frame on the platform, and which detection is used to control the movement of the plate-like supports. A wire bonding apparatus employs two of such transfer devices on either side of a wire bonding head. Transfer rails extend past the transfer devices.

Abstract: After specific data are stored at individual page latches 80.sub.1 to 80.sub.m, the latch data stored at the page laches 80.sub.1 to 80.sub.m are written into one-word memory cells 10.sub.1j to 10.sub.mj.When the data writing is completed, the individual sets of latch data stored at the page latches 80.sub.1 to 80.sub.m are output to bit lines BL.sub.1 to BL.sub.m, to be compared against the memory data stored in the individual memory cells 10.sub.1j to 10.sub.mj.These comparison results are re-stored at the individual page latches 80.sub.1 to 80.sub.m. At this point, if the memory data stored in the memory cells 10.sub.1j to 10.sub.mj have been written correctly, L level data are written at the corresponding page latches 80.sub.i, whereas if they have not been written correctly, H level data are written at the page latches 80.sub.i.The data that have been re-stored at the individual page latches 80.sub.i are output to a data verification line DL to which a verification unit 100 is connected.

Abstract: A high voltage MOS (Metal Oxide Semiconductor) transistor includes a semiconductor substrate of first conductivity type (P type). A pair of first diffused layers of second conductivity type (N type) are formed on the substrate. A pair of second diffused layers of second conductivity type (N type) are respectively formed in the first diffused layers and have a higher concentration than the first diffused layers. A gate region intervenes between the two first diffused layers facing each other. The gate region consists of a gate oxide film and a gate electrode. The distance between the first diffused layers is smaller in the deep region of the substrate than at the surface of the substrate. The MOS transistor has a great breakdown resisting quantity.

Abstract: A semiconductor device 10 enables efficient use of semiconductor wafer and higher productivity by splitting an electric circuit function into a plurality of semiconductor chip portions 12 and interconnecting the plurality of semiconductor chip portions 12 on a single carrier tape.

Abstract: An output circuit of a semiconductor memory device is made up of a level recognition circuit which outputs a feedback signal by comparing an output node and a second reference voltage, and a P-channel MOS transistor and an N-channel MOS transistor which complimentary turn on and off in response to the feedback signal. As a result, when a charge of the output node is not sufficient, the output node is charged by setting a voltage of a power supply node to a power supply voltage Vcc. Then, when the output node is sufficiently charged, the N-channel MOS transistor turns on, and as a result the voltage of the power supply node is set to a first reference voltage. Accordingly, the output circuit of the semiconductor memory device achieve an increased operation speed and decreased voltage level amplitude at the output node.

Abstract: A wafer loading-state inspection apparatus includes a transmissive wafer sensor including a light emitter and a light detector. The light emitter is spaced apart from the light detector in a horizontal plane by a predetermined separation distance. The wafer sensor generates wafer pulses indicating whether a wafer is detected between the light emitter and the light detector. A wafer sensor support has a first arm connected to the light emitter and a second arm connected to the light detector. A vertically oriented post is connected to the wafer sensor support at one end. Connected at the other end of the post is a driving mechanism which produces a reciprocating vertical movement of the post over a vertical range.

Abstract: In a semiconductor memory having bit lines 10 for data input/output for a memory cell formed at the surface of a semiconductor substrate 1, grooves 19 extending along the direction of the wiring of the bit lines 10 are formed at an oxide film 18 with the bit lines 10 provided connected to the grooves 19. Since the bit lines 10 are made to connect to the grooves 19, the bit lines 10 are firmly secured to the oxide film 18. Thus, the bit lines 10 do not move even when stress is applied to their side surfaces during a heat treatment.

Abstract: A polymer for use in making a chemically amplified photoresist, a photoresist composition containing the polymer, and a method of preparing the same. The polymer for a photoresist is formed by polymerizing three or more different monomers and it has an acid-labile di-alkylmalonate group bound to the backbone of the polymer. The polymer can be used to form a photoresist composition that includes the polymer and a photosensitive acid generator. The photoresist composition is suitable for forming a pattern having an excellent profile due to the high contrast and high thermal decomposition temperature of the photoresist composition.