Abstract: A vacuum dryer and a method of drying a semiconductor device using the same are provided. In the present invention, a vacuum dryer using isopropyl alcohol vapor, including an outer bath, an inner bath, a main water supply line, a supplementary water supply line, an inner bath drain line, and an outer bath drain line, is provided. After cleaning the inside of the vacuum dryer, the inner bath is filled with the supplied deionized water and the deionized water is continuously overflowed. Then, the semiconductor substrate is loaded into the inner bath of the vacuum dryer to which the deionized is continuously overflowed. The loaded semiconductor substrate is dried by supplying the isopropyl alcohol vapor to the inner bath into which the semiconductor substrate is loaded.

Abstract: A test board for testing a semiconductor IC device has a plurality of device attachment pads which are to be electrically connected to a plurality of I/O pins of the semiconductor IC device, a plurality of land pads which are to be electrically connected to a plurality of probe pins of a testing apparatus, a plurality of signal wires electrically connecting the device attachment pads to the land pads, and a plurality of power supply wiring patterns for supplying power to the semiconductor IC device. The power supply wiring patterns include both internal power supply wiring patterns which are disposed radially inwardly of the device attachment pads, and external power supply wiring patterns which are disposed radially outwardly of the device attachment pads. When set up for testing, an IC socket is mounted to the test board.

Abstract: A flat, surface mounted, flexible, multi-purpose wire has a plurality of flat elongated conductors spaced apart in a generally parallel relationship. Each of the flat conductors includes a plurality of conductive layers. At least one optical fiber lies lengthwise in a plane between the flat conductors. An adhesive material separates the flat conductors and an insulation layer surrounds the flat conductors and the adhesive material, with the adhesive material bonding to the insulation layer. A cross-sectional height of the flat conductors and insulation layer is such that the multi-purpose wire will blend in with the surface when painted or after wallpaper is applied.

Abstract: A printed circuit board (PCB) for use in chip-on-board (COB) packages reduces failures due to warping of the COB packages. The PCB includes a board body having a upper surface and a lower surface, a chip bonding area on the upper surface for attaching a semiconductor device, and a plurality of conductors in a circuit pattern on the upper surface outside the chip bonding area, for electrical connection to the semiconductor device using a plurality of bonding wires. An encapsulation region encloses the chip bonding area, the bonding wires, a portion of the plurality of conductors, and a portion of the upper surface. The board includes external contacts on the lower surface for electrical connections to an external electrical appliance, and via holes through the board body for electrically connecting the plurality of conductors in the circuit pattern to the external contacts.

Abstract: A method for forming an interconnection in a semiconductor element includes a process for forming a groove on an underlying substrate so as to correspond to the designed pattern of the interconnection. An underlayer for improving crystalline orientation of the interconnection is formed on the underlying substrate having the groove. A thin film of interconnection material is formed in the groove and a heattreatment process is carried out to ensure that the groove is filled with the thin film of the interconnection material. Formation of the interconnection is completed by polishing the surface of the thin film by a predetermined quantity.

Abstract: In a non-volatile memory, memory cells have respective floating gates formed of a first polysilicon and respective control gates formed of a second polysilicon. Further, in the non-volatile memory, peripheral circuits include transistors having respective gates formed of the first polysilicon. In addition, a silicide layer is formed directly on the control gates of the memory cells and directly on the gates of the transistors.

Abstract: A semiconductor device that enables a reduction in power consumption and a stable operation, and which can be manufactured easily and with a high level of integration.In an invention exemplifying the present application, a sense circuit constituting a DRAM comprises a bit line pre-charge circuit, a pre-amplifier circuit PSA100 and a main amplifier circuit MSA100. The pre-amplifier circuit is provide with a switch circuit and an amplifier circuit. The switch circuit comprises a switch element provided between input/output terminals and a pre-sense node, and a switch element provided between input/output terminals and another pre-sense node. The amplifier circuit comprises MOS transistors and switch elements.

Abstract: A rectifier circuit 30 of a voltage genetator rectifies alternating current signals provided through electromagnetic induction of a coil. The rectified signals are boosted by rectifying the voltage of nodes of the coil by capacitors, and the voltage genetator generates a predetermined voltage by smoothing the boosted signals using a capacitor.

Abstract: A boat for semiconductor wafers has reduced contact surface area with the wafer, thereby preventing distortion of the wafer during heating. The boat has an upper member; a lower member, a plurality of wafers being loaded between the upper member and the lower member; and a plurality of support members vertically extended between and connecting the upper member to the lower member for supporting the wafers. A plurality of slots are successively and horizontally formed in each of the support members, and the peripheral edge of the wafer is inserted therein, wherein a hemisphere-shaped protrusion is formed inside the slot, and the bottom surface of the wafer contacts and is supported by each hemisphere-shaped protrusion at a single contact point.

Abstract: A matrix-type display capable of being repaired by pixel unit, Two or more of signal lines such as scanning lines, image signal lines and auxiliary signal lines and a pixel electrode are overlapped via an insulating layer, so that a defect such as the disconnection of the image signal lines and scanning lines, the short of the pixel electrode and the signal line, and the loss of electrode of a switching element, and a pixel defect can be repaired. Here, the layout of the auxiliary gate line and dual gate line can be modified.

Abstract: A method of in-line monitoring for shallow pits formed on a semiconductor substrate using an electron beam. The electron beam is scanned across exposed pads on the semiconductor substrate and relative concentrations of secondary electrodes are examined to identify shallow pits.

Abstract: A wafer aligning apparatus for semiconductor device fabrication includes a cassette support on which is mounted a cassette holding wafers immersed in a non-conducting fluid. A guide roller is composed of carbon fiber reinforced polyether and rotates in contact with circumferential edges of the wafers.

Abstract: The phosphorus concentration of an upper electrode and the phosphorus concentration of a lower electrode can be made equally high without loss of adhesion between the polysilicon and a metallic layer. It includes a step of forming a stacked layer structure consisting of: a lower electrode layer provided on an underlay, a dielectric layer provided on this lower electrode layer, and an upper electrode layer consisting of an impurity-doped layer and a metallic layer successively provided on this dielectric layer, and a step of doping the metallic layer with the same impurity as the impurity in the impurity-doped layer prior to heat treatment of the stacked layer structure.

Abstract: A semiconductor memory of wherein the delay of control signals for controlling sense amplifiers is efficiently controlled, without extensively changing a currently-used fabricating process. A dummy bit line pair are arranged between desired bit line pairs in the memory cell array. Since the dummy bit line pair is not related to a normal operation such as reading data stored in memory cells, it is not necessary to dispose a sense amplifier in an area of a sense amplifier array adjacent to the dummy bit line pair. As a result, there is formed a free area in the sense amplifier array. The free area has at least a width between the dummy bit line pair. This free area further forms a contact portion for electrically connecting sense amplifier control signal lines and low resistance sense amplifier control signal lines. That is, this free area is utilized as a shunt area of the sense amplifier control signal lines.

Abstract: A monitoring device and a driving control system for a fan filter unit in a semiconductor clean room for monitoring the operating state of the fan filter unit. The monitoring device includes a switching section in each fan filter unit which alternately applies electrical power to one of a plurality of terminals. The switching section is responsive to a force from an air stream introduced therein via rotation of a fan in the fan filter unit. A display section in each fan filter unit is connected to the plurality of terminals which provide different signals, indicative of an on or off state of the fan, according to which of the plurality of terminals is electrically connected to the electrical power.

Abstract: A multiple tubular shaped capacitor electrode of a semiconductor capacitor with an increased surface area and a method for fabricating thereof. The multiple tubular shaped capacitor includes at least two tubular shapes whose side portions are overlapped with each other. The multiple tubular shaped capacitor is made by forming an insulating layer over an etch stop layer including a contact plug, partially etching the insulating layer down to the contact plug and etch stop layer to form an opening composed of at least two upright cylindrical openings with side portions that define an overlap, and forming a conductive layer on a bottom and both side walls of the opening to form a storage node composed of at least two upright tubular shapes which are attached together at a vertical side section which defines an overlap portion of both tubular shapes to form a capacitor storage node.

Abstract: A dry etching apparatus used for manufacture of a semiconductor device includes a plasma confinement ring secured by screws to a cathode, an anode, and a metal focusing ring extending around the anode for enhancing the uniformity of the plasma. The screws are located a maximum distance away from the focusing ring. Thus, micro-arcing is prevented from occurring between the focusing ring and the screws. The confinement ring is also designed to distribute the plasma stream only onto the wafer, so that the generation of contamination particles is suppressed during etching.

Abstract: Disclosed herein is a microcomputer of the present invention.

Abstract: A fan drive checking system, for an air conditioning system in a clean room having a fan filter unit (FFU), includes a flow sensor for sensing air flow inside a housing of a FFU. The sensor provides a sensor signal indicative of normal and adverse flow conditions in the housing. A control portion in data communication with the sensor outputs a control signal responsive to the sensing signal. An alarm in data communication with the control portion provides a warning when the control signal indicates the adverse flow condition.

Abstract: A gas mixture for etching a polysilicon electrode layer in a plasma etching apparatus, and a method for etching the electrode layer using the same. The etching gas mixture is a mixture of Cl.sub.2 gas and N.sub.2 gas, wherein the N.sub.2 gas is in the range of about 30% by volume of the total volume of Cl.sub.2 gas and N.sub.2 gas combined. In the electrode layer etching method of the present invention, the polysilicon electrode layer is formed on a semiconductor substrate. A mask pattern of an oxide or photoresist is then formed on the electrode layer. The electrode layer is etched using a plasma formed by the gas mixture of Cl.sub.2 gas and N.sub.2 gas, with the mask pattern functioning as an etching mask. An upper power source of the plasma etching apparatus delivers power in the range of about 500 to 1000 W, while the etching gas mixture is formed by supplying Cl.sub.2 gas at a rate of about 100 to 400 sccm, and N.sub.2 gas at a rate of about 3 to 15 sccm.