Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

Abstract: A method of and software for booting a network computer with universal boot code is disclosed. Initially, the type of a boot device is determined from among a set of possible boot devices. A command in a high level boot code segment of the boot code software is then translated to a command executable by the boot device based upon the determined device type. The converted command is then executed on the boot device to transfer data between the network computer and the boot device. The boot code is preferably compatible with a variety of boot devices including a hard disk boot device, an NFS server boot device, as well as a TFTP server boot device. In an embodiment in which the boot device is a TFTP boot device, a READ command from the high level boot code is translated to a TFTP read request. The data transferred by the TFTP read request may be stored in a file cache on the network computer.

Abstract: A mobile computing device and associated base stations are disclosed. The mobile computing device includes a system-on-chip (SOC) device that includes a general purpose processor core and a plurality of peripheral cells suitable for controlling a plurality of peripheral units. The mobile computing device further includes a system memory and a base unit interface. The base unit interface is suitable for connecting the mobile computing device to a base unit that includes a display adapter suitable for controlling a video display. The SOC is connected to and enabled to control the display adapter when the mobile computing device is connected to the base unit. The base unit interface may comprise a PCI interface that connects the SOC device to the base unit via a PCI bus. The plurality of peripheral units may include an audio adapter, a flash device, a wireless suitable for transmitting and receiving wireless information, and a liquid crystal display suitable for displaying text messages.

Abstract: A method, system, and computer program product for emulating a sequence of events resulting from user interaction with an applet in which the storing and retrieval of queued event objects is facilitated through the use of an index to a component vector. When an applet event recorder is invoked and the applet selected, an automator initializes the applet and generates a component vector that includes a reference to each component of the applet. Events are then detected by the applet event recorder via automator listeners. The automator then generates queued event objects and stores the queued event objects in an automator queue. The generation of queued event objects in one embodiment includes the generation of a component index value that points to the component of component vector that references the applet component that was responsible for generating the corresponding user interaction event.

Abstract: A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer.

Abstract: A method and system for controlling access to an adapter, such as a graphics adapter, are disclosed. The method includes querying an adapter lock with a first thread. Thereafter, responsive to determining that the lock indicates the first thread does not have access to the adapter, a sequence to obtain access to the adapter is initiated where the sequence includes writing the adapter context corresponding to the first thread. The, sequence may include a ring 3 to ring 0 transition. The method also includes, in response to determining that the lock indicates the first thread has access to the adapter, communicating to the adapter with the first thread without invoking the sequence to obtain access to the adapter. In one embodiment, querying the adapter lock includes writing a first word of the adapter lock using an atomic operation.

Abstract: A conveying system including multiple conveying tracks where each track acts as the output track from one operation and the input track to a subsequent operation. When the manufacturing process at a first operational area is completed, the completed product is placed on the area's output track and conveyed to a subsequent operational area. When the processing at the subsequent area is completed, the unit is placed on the subsequent area's output track, which is a physically distinct track from the area's input track. The input and output tracks within an operational area may occupy different levels of a multi-level system in which the various levels share a common floor space footprint to conserve floor space requirements. The tracks may be configured as a pair of tracks to facilitate simultaneous processing of two products or jobs. In addition, one or more of the tracks may have a support surface that is not parallel to the manufacturing floor.

Abstract: A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle.

Abstract: A method and an associated system and computer program product for determining sequences suitable for testing an electronic system that is comprised of a set of nets. Each net of the system provides an interconnect between a set of nodes. The method includes a step in which nodes that are enabled by a common enable latch within the system are identified. Each commonly enabled node is associated with a node group. Each node group includes the set of nodes that share a common enable latch. Contending node group pairs within the system are then identified. A contending node group pair is any pair of node groups in which at least one commonly enabled node of the first node group and at least one node of the second node group reside on a common net. Sequence numbers, preferably for use in defining a boundary scan test sequence, are then assigned to each commonly enabled node in the system.

Abstract: A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.

Abstract: A floating point to fixed point converter suitable for determining values for an n-bit frame buffer of a graphics adapter is disclosed. The converter includes a floating point unit that receives a floating point input value and calculates a floating point adjusted input value from the received value. Comparator circuitry is configured to compare a fixed point portion of the adjusted input value to a fixed point comparison value and to generate a fixed point output value responsive to the result of the comparison. The floating point unit may add a floating point constant to the received input to calculate the adjusted input value. The floating point constant may include a rounding component and a range component. The range component adjusts received values into a range defined by a single floating point exponent value such as the range from 1.0 to 2.0.

Abstract: A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information.

Abstract: A wafer carrier (300) for a CMP tool is adjustable to provide center fast to edge fast material removal from a semiconductor wafer. The wafer carrier (300) holds the semiconductor wafer without vacuum. The semiconductor wafer is held by a carrier ring (308). An elastically flexed wafer support structure (318) is a support surface for the semiconductor wafer. Elastically flexed wafer support structure (318) can be bowed outward or bowed inward in an infinite number of different contours. The semiconductor wafer conforms to the contour of the elastically flexed wafer support structure (318) when a down force is applied to the wafer carrier (300) during a polishing process. Changing the contour is used to produce different material removal rates across the radius of the semiconductor wafer to increase wafer planarity in a polishing process.

Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

Abstract: A system, device, and method for dynamically testing integrated circuits is disclosed. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state.

Abstract: A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state.

Abstract: A heat sink retention assembly including a spring, a spring retainer, and a spring displacement limiter. The spring retainer maintains the spring in a compressed state in which a contact portion of the spring applies a force to the heat sink. The compressed state is characterized by a predetermined spring displacement and exerted force. The spring displacement limiting mechanism prevents displacement of the compressed spring substantially beyond the predetermined spring displacement. The displacement limiting mechanism may comprise a separate component such as a spacer structure or may be integrated into the configuration of the spring itself. In one spacer structure embodiment, the spacer has a vertical dimension that is determined by the difference between the total spring displacement possible and the predetermined spring displacement required to deliver the predetermined force to the heat sink.

Abstract: A method and circuit for summing multiples vectors is disclosed. The method includes receiving a set of input vectors and generating a set of decoded summation vectors. Each of the set of decoded summation vectors indicates the value of at least a portion of the vector sum. The method further includes generating a set of decoded carry vectors. Each carry vector is used to select the summation vector for an adjacent portion of the vector sum from a set of preliminary summation vectors. In one embodiment, the method further includes counting the number of high bits in each bit position of the input vectors and generating decoded high bit count vectors based upon the counting to facilitate the generation of decoded summation vectors. In one embodiment, the set of preliminary vectors includes an initial preliminary summation vector and a set of adjacent summation vectors. In this embodiment each adjacent summation vector is achieved with a 1-bit rotation of the preceding adjacent summation vector.

Abstract: A method, system, and computer program product for preserving events generated from user interaction with an applet including the ability to record and manipulate delay information associated with the user interaction, sequence. User interaction events, including timing information associated with each event, are detected by the recorder via automator listeners. An automator then generates queued event objects including delay information computed from the timing information of each event where the delay information indicates the amount of time that elapsed between the posting of consecutive events during the original user interaction sequence. A timing mode is then selected from the mode section of a graphical user interface and an emulated sequent including a set of constructed objects produced by automator from the queued event objects is generated.

Abstract: A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals.