Abstract: A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch.

Abstract: A cable suitable for use in a data processing network is disclosed. The cable includes an electrically insulating shielding, a signal carrying element enclosed by the shielding, and an identifying element embedded in the shielding. The identifying element is suitable for transporting light from a first end of the cable to a second end and for externally emitting the light at the second end. The signal carrying element be implemented as a twisted wire pair, a coaxial cable, or an optical fiber. The identifying element may include an optical fiber that is connected to a lens embedded in the shield at the second end of the cable. The first end of the optical fiber may be connected to another lens that is embedded in the shielding at the first end of the cable. Alternatively, the first end of the optical fiber may be connected to an LED, which is connected to a circuit including a battery aid a contact switch.

Abstract: A method, system, and computer program product for recording events that result from user interaction with the various components of an applet, such as a Java applet. An applet event recorder is invoked and associated with an applet, preferably via a graphical user interface. One or more types of events are then selected for recording via a recording options section of the graphical user interface. When a user interaction sequence with the applet occurs, events of the selected type are then detected by the applet event recorder. An automator of the applet event recorder then generates and stores the queued event objects in an automator queue. The automator then generates, presumably at a later time, constructed events from the queued events in the automator queue. The constructed events are then played back by posting them in the system queue thereby achieving the recording and playback of selected events.

Abstract: A texture image that comprises a set of texels wherein each texel is assigned a (u,v) coordinate pair of a texture coordinate space. Each texel is then stored in memory at a memory address determined by applying a transformation function to the texel's (u,v) coordinate pair. The transformation function is customized to associate two dimensional portions of the texture coordinate space to each page of memory. When the texture image (or a portion of the texture image) stored in memory is later mapped to an object during rendering the object, the allocation of two dimensional portions of the texture coordinate space to each memory page reduces the number of memory pages accessed during the rendering of the object. The reduction in the number of memory pages accessed during the texture mapping process translates into improved texture mapping performance.

Abstract: A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer (20) over a semiconductor substrate (10). A thermodynamically stable dielectric layer (22) is then formed over the lattice matched dielectric layer (20). A semiconductor layer (30) is then formed over the thermodynamically stable dielectric layer (22). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate (50) to the semiconductor layer (30). The first semiconductor substrate (10) is then removed to expose the lattice matched dielectric layer (20). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.

Abstract: A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage states. A set of verification directives based on the set of missing coverage states is composed and a set of test cases is generated, based on the verification directives, to simulate the missing coverage states. Analyzing the verification coverage information may include decomposing the verification coverage information into a set of basic coverage tasks (BCTs), wherein each BCT is a generic representation of a corresponding task. Decomposing the verification coverage information into a set of BCTs may comprise decomposing the verification coverage information into a set of covered BCTs and a set of BCT holes, wherein the covered BCTs represent verification states covered by the simulation and BCT holes represent verification states not covered.

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

Abstract: A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks.

Abstract: A system, conferencing application, and graphical user interface for supporting standards based, multiparty teleconferencing, video conferencing, and application sharing are disclosed. The system includes a hardware platform such as a desktop computer, a network computer, or a workstation computer. The hardware platform includes one or more processors, and a system memory as well as input and output devices for user interaction. Conferencing hardware such as a microphone and speakers for audio content and a video camera for video content are interfaced to the hardware platform, typically through an I/O bus of the hardware platform. The system further includes operating system software residing at least in part in memory. The operating system controls execution of application programs on the hardware platform. The system further includes an application for participating in a multi-party conferencing session.

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.

Abstract: A method, system, and computer readable medium for synchronizing performance monitors in the multiprocessor system are disclosed. The system includes a lead processor and at least one slave processor. The method includes informing the slave processor that a synchronization signal is forthcoming and waiting for an acknowledgment indicating that the slave processor is ready to receive the synchronization signal. In response to the slave processor's acknowledgment, the method includes sending the synchronization signal to the slave processor. The lead processor's performance monitors are set when the synchronization signal is sent and the slave processor's performance monitors are sent when the synchronization signal is received by the slave processor. In one embodiment, informing the slave processor that a synchronization signal is forthcoming is achieved by issuing a first inter-processor interrupt.

Abstract: A computer system including a central processing unit and a system memory accessible to the central processing unit via a host bus. A primary non-volatile storage element and a backup non-volatile storage element are incorporated into the system's motherboard. The primary non-volatile storage element contains the system's boot code that is executed following a reset or power on event. The backup non-volatile storage element contains a restoration sequence that is suitable for reprogramming a first portion of the boot code in the primary non-volatile storage element. A jumper block on the motherboard determines which of the non-volatile storage elements is initially addressed following a power on event. Preferably, the first portion of the boot code comprises the system's boot block or gold code and includes a sequence for downloading and reprogramming remaining portions of the boot code. The primary non-volatile storage element is preferably implemented as a multiple sector flash memory device.

Abstract: A network computer including, a chassis, a power supply affixed to an interior surface of the chassis, a motherboard powered by the power supply, the motherboard including a clock generator, a boot code storage device, a processor, and a system memory, and a network interface suitable for interfacing the network computer to a server computer via a network. The network computer lacks a disk drive, but includes local permanent storage such as a compact flash card. Preferably, the network computer includes one or more peripheral devices connected to a peripheral bus of the computer. In the preferred embodiment, the network interface provides is an Ethernet compliant connection with an RJ45 connector. In one embodiment, the power supply powers the motherboard via a single power plane. In one embodiment, the network computer includes disk drive facilities for receiving a disk drive.

Abstract: A computer network and network client where the network client includes a nonvolatile storage device for storing a packet replication indicator and a third party host identifier. The client further includes means for modifying the state of the packet replication indicator and the third party host identifier. The client has means for initiating a boot code sequence stored on a client boot code storage device. If the client detects a specified state of the packet replication indicator, the boot code sequence establishes a communication socket with a third party host identified by the third party host identifier and forwards copies or replicates of packets that are exchanged between the network client and a network server. In one embodiment the packets are replicated to the third party host until the boot sequence terminates. The third party host identifier is preferably comprised of an IP address portion and a third party host port identifier portion.

Abstract: A device such as a tape drive or disk drive unit and a computer system that incorporates the device in which he device preferably includes a controller or processor and a non-volatile storage element configured with microcode suitable for execution by the controller. In an embodiment suitable for use in the computer system, the controller is preferably configured for communicating with a peripheral bus of a computer system via a bus interface unit. The device further includes a non-volatile fault indicator and fault logic suitable for detecting a fault condition in the device. The fault logic is adapted to program the non-volatile fault indicator upon detecting a fault condition to preserve the occurrence of the fault. In this manner, both repeatable and intermittent fault conditions are documented for subsequent servicing by a service engineer.

Abstract: A multiprocessor computer system including a set of processors where each processor in the set includes an execution unit for issuing operations and a processor queue suitable for queuing previously issued and still pending operations. The multiprocessor further includes means for forwarding operations issued by the processor to the processor queue and to an operation block queue of a memory subsystem that is connected to the multiprocessor. The depth of (i.e., the number of entries in) the operation block queue matches the depth of the processor queue. The processor queue, when full, inhibits the processor from issuing additional operations. In this manner, an operation issued by the processor is guaranteed an available entry in the operation block queue of the memory subsystem thereby eliminating the need for operation retry circuitry and protocols such as handshaking.

Abstract: A connector for use in a network interface including a connector housing, preferably formed of a conductive material such as aluminum. The housing includes a receptacle face that defines a receptacle opening. A receptacle of the connector is attached to an interior surface of the housing and suitable for receiving a terminus of the network cable through the receptacle opening. The connector has a connector circuit including a cable port coupled to the network cable and an interface port coupled to the network interface. The housing defines at least one conduit adapted for receiving a light pipe. Preferably, the network interface provides an Ethernet connection. In one embodiment, the connector circuit includes magnetic components. In the preferred embodiment, the connector comprises an RJ45 connector. The invention further contemplates a network interface integrated within a motherboard, a connector affixed to the mother, an LED attached to the motherboard, and a light pipe.

Abstract: A computer system and an associated graphics adapter that includes one or more processors connected to a host bus. A system memory is accessible from the host bus via a memory controller and an I/O bridge is coupled between the host bus and an I/O bus. The computer system further includes a frame buffer suitable for storing a representation of a graphic image and the graphics adapter connected to the I/O bus. The graphics adapter includes means for receiving host pixel data that is formatted, according to a host format defining the ordering and width of a set host components, as a set of host component values. The adapter also has means for transforming the host pixel data into frame buffer pixel data where the frame buffer pixel data is formatted, according to a frame buffer format defining the ordering and width of a set of frame buffer components, as a set of frame buffer component values.

Abstract: A retention apparatus (hanger) suitable for use with a data processing system that includes a data processing box and a video display is disclosed. The hanger includes a pair of substantially parallel major sides and a pair of substantially parallel minor sides that connect the pair of major sides at their respective ends to define a substantially rectangular aperture suitable for receiving the data processing box. The hanger further includes a hook that has a base portion and a tooth portion connected at an end of the base portion. The base portion extends substantially from and in line with one of the minor sides such that the tooth portion is laterally displaced from one of the major sides with the tooth oriented towards the other minor side. In this configuration the hook enables the hanger to suspend from a groove in the display monitor with the first major side of the hanger in close proximity to a rear face of the video display.

Abstract: A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit.