Abstract: A frequency modulated signal is converted into a pair of baseband signals by mixing the signal with a pair of phase-quadrature reference signals of substantially carrier center frequency. The double reference frequency component of each of the baseband signals is filtered to obtain I and Q signals. The I and Q signals constitute in rectangular coordinates the components of a vector represented in polar coordinates by R and .theta. where R is the maximum amplitude of the I and Q signals and .theta. is the instantaneous angle represented by the arctangent of the I signal divided by the Q signal. The I and Q signals are inverted to provide respective -I and -Q signals. The I, -I, Q, -Q signals are sampled to provide a sequence of sets of signal samples. For each set of signal samples the angle .theta. is obtained. A sequence of changes in the values of the angle .theta.

Abstract: A transistor is formed about a recess in the planar surface of a substrate of silicon. A pair of insulating spacers is provided in the recess, each abutting a respective side of the recess. Gate oxide is formed in the recess between the insulating spacers. A gate electrode is provided having one base overlying the gate oxide and the other base substantially coplanar with the planar surface. A source region extends from one side of the channel underlying the gate oxide to the planar surface. A drain region extends from the other side of the channel underlying the gate oxide to the planar surface.

Abstract: A first video signal is provided comprising a plurality of lines of a luminance signal, a first color signal and a second color signal, each of the lines having a duration of a first predetermined time. Each of the nonoverlapping pairs of successive lines of the luminance signal are summed and differenced to provide a luminance sum signal and a luminance difference signal. Each of the nonoverlapping pairs of successive lines of the first color signal and also of the second color signal are summed to provide a first color sum signal and a second color sum signal. The luminance difference signal, the first color sum signal and the second color sum signal are bandwidth limited in relation to the luminance sum signal. Corresponding lines of these signals are time compressed to the same bandwidth and then time multiplexed to form a corresponding line of a first compound signal, each line of which has a duration of the aforementioned predetermined time, and alternate lines of which have zero amplitude.

Abstract: A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter.

Abstract: A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs.

Abstract: A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substrate. The cell includes a latch comprising a complementary pair of IGFETs for actively storing one binary logic state. For storing the other binary logic state, there is only a single pull-up transistor connected to one data node and a high-impedance leakage current discharge path for the other data node. The cell also includes a pair of input/output gating transistors connected to the data nodes and operating in push-pull. Various forms of high impedance leakage current discharge path are disclosed, none of which require any increase in chip area.

Abstract: A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node.

Abstract: An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and Q data output nodes to +V.sub.DD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.

Abstract: A system is described which makes use of the fact that in a raster scanned television system a high degree of correlation exists both in the luminance and in the chrominance signals of a pair of adjacent lines. Because of this correlation, the difference between the luminance signals of the two lines is usually much smaller than the luminance signal of either line alone, and requires less bandwidth. A luminance carrier is amplitude modulated by the average value of two adjacent lines, while the phase of the carrier is modulated by the difference of two adjacent lines. The bandwidth of the resulting signal is comparable to that of a carrier that is amplitude modulated by a single raster line. Since two lines of information are being transmitted, however, it would be possible to take twice as much time to transmit them as when only a single line is being transmitted. Stretching the time axis in this way results in a factor of about two reduction in bandwidth.

Abstract: A shift register using dual gate transistors is described. Each stage consists of a P-channel and and N-channel dual gate transistor interconnected to provide both an inverting function and a switching function. The gates of each stage of one set of alternate stages are clocked in one phase with a clocking voltage alternating between a low level and a high level and its inverse. The gates of each stage of the other set of alternative stages are clocked in the opposite phase with the clocking voltage and its inverse.

Abstract: The resistivity of a conductor of a refractory metal such as molybdenum is reduced by converting at least a portion of the conductor into a layer of molybdenum nitride in an atmosphere including ammonia at a temperature in the range from about 400.degree. C. to about 850.degree. C. and thereafter heating the conductor in an atmosphere including dry hydrogen in the range from about 950.degree. C. to about 1000.degree. C. for a time to convert the layer of molybdenum nitride into molybdenum and to convert molybdenum oxides in the conductor into molybdenum.

Abstract: Dual gate P-channel and N-channel transistors are interconnected in various configurations to provide logic circuits such as inverters, NAND gates, NOR gates, and Exclusive-OR gates.

Abstract: In semiconductor imaging apparatus a composite electrode structure which transmits a high percentage of the radiation incident thereon and which also has high electrical conductivity is provided as the first level of a two level electrode structure.

Abstract: A plurality of charge storage cells, each including first and second storage regions and corresponding first and second electrodes insulatingly overlying the storage regions are provided in a semiconductor substrate. Means are provided for introducing into each of the first charge storage regions a respective quantity of charge proportional to a respective sample of an analog signal. Means are provided for developing a plurality of voltage waveforms, each of the waveforms including a series of periods, and each period constituted of first and second subperiods. Means are provided for applying each of the voltage waveforms to a respective one of the second electrodes of the cells.

Abstract: A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of ammonia in the range from about 400.degree. C. to 850.degree. C. for a time to cause the atmosphere to react with the conductor to convert a portion of the conductor into molybdenum nitride.

Abstract: Apparatus is disclosed for uniform exposure of a plurality of objects such as semiconductor wafers to radiation utilizing sources of radiation of linear configuration. The apparatus includes a baffle assembly of particular construction and constitution situated between the linear sources and the region to be irradiated.

Abstract: A method of making an integrated circuit is described. The method includes providing a substrate of single crystal silicon semiconductor material having low minority carrier lifetime, forming an insulating layer of silicon dioxide overlying a major surface of the substrate, forming a plurality of apertures in the insulating layer which expose a plurality of selected portions of the major surface of the substrate, and epitaxially growing a layer of silicon on each of the selected portions of the major surfaces of the substrate.

Abstract: The correlator includes a plurality of charge storage cells, each including first and second storage regions and corresponding first and second electrodes insulatingly overlying the storage regions.Into each of the first charge storage regions a respective quantity of charge proportional to a respective sample of an analog signal is introduced. A series of voltage waveforms are developed each successive waveform being identical to the period of a preceding waveform except delayed by the period of a cycle of the waveform in response to a digital reference word.Each of the voltage waveforms are applied to a respective one of the second electrodes of the cells for controlling the transfer of charge between the first and second charge storage regions thereof, a transfer in one direction representing a multiplication of an analog sample by +1 and a transfer in the other direction representing a multiplication of an analog sample by -1.

Abstract: A method of defining in a substrate of silicon an active region, a region of field oxide and an isolating wall of silicon dioxide therebetween in a single masking step. The substrate is covered in succession with a thin layer of silicon dioxide, a thick layer of silicon nitride and a first film of titanium. The first film of titanium is covered with a layer of photoresist which has a removed portion and a retained portion in registry with the active region. The first film of titanium and the layer of silicon nitride are etched through the removed portions of the layer of photoresist to form an opening extending to the thin layer of silicon dioxide and partially underlying the retained portion of the photoresist layer by a predetermined lateral distance. A second film of titanium is deposited on the retained portion of the photoresist layer and the exposed portion of the thin layer of silicon dioxide.

Abstract: A filter utilizing charge transfer devices for providing recursive transfer functions is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, a first charge transfer shift register, and a second charge transfer shift register. A first input stage is unidirectionally coupled to the first stage of the first shift register and is also bidirectionally coupled to the N.sup.th stage of the circular shift register. A second input stage is unidirectionally coupled to the first stage of the second shift register and is also bidirectionally coupled to the (N/2).sup.th stage of the circular shift register. A first input sequence of packets of charge representing positive weight components of a signal is applied to the first input stage and a second input sequence of packets of charge representing negative weight components of the signal is applied to the second input stage. All three shift registers are clocked at the same frequency.