Abstract: A composite conductive structure in integrated circuit devices is described. The composite conductive structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide. A layer of a silicide of the refractory metal covers the conductor and a layer of silicon dioxide covers the layer of the silicide. A method of making such structures is also described.

Abstract: A filter utilizing charge transfer devices and having resonant transfer characteristics is described. The filter includes a first charge transfer shift register including a plurality of stages to which a first sequence of packets of charge is serially applied and clocked from stage to stage. Charge division and collection means are provided at the various stages of the shift register to divide and collect fractions of charge appearing in the various stages thereof. The charge collection means of the various stages except the last are connected together to provide a first output representing the sum of the charges collected at the various stages thereof. These fractions represent the weighting coefficients of the various stages of the first shift register. A second charge transfer shift register identical to the first shift register is provided. A second sequence of packets of charge is serially applied to the second shift register and clocked from stage to stage.

Abstract: A sampled data transversal filter utilizing charge transfer devices is described. The filter includes a charge transfer shift register including a plurality of stages to which a sequence of packets of charge representing samples of a signal is serially applied and clocked from stage to stage. Charge division and collection means are provided at the various stages of the shift register to divide and collect the fractions of charge appearing in the various stages thereof. These fractions represent the weighting coefficients of the various stages of the shift register. The charge collection means of the various stages are connected together to provide an output representing the sum of the charges collected at the various stages. The output sequence of packets of charge obtained represent the convolution of the input sequence of packets with the weighting coefficients of the various stages of the shift register.

Abstract: A filter utilizing charge transfer devices for providing recursive transfer functions is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, and first and second linear charge transfer shift registers. A composite stage of the first linear shift register is coupled to the N.sup.th stage of the circular shift register through a first gating means. A composite stage of the second shift register is coupled to the ##EQU1## stage of the circular shift register through a second gating means. A first sequence of packets of charge is applied to the first shift register, and a second sequence of packets is applied to the second shift register. All three shift registers are clocked at the same frequency. At the end of each clocking cycle the first gating means is operative to combine the charge stored in the N.sup.

Abstract: Apparatus is described for the generation of a series of binary numbers which has a minimum value other than zero, has a major sequence of numbers in which successive numbers are separated by a first fixed increment starting from the minimum value and defining the range of the series of numbers, and has a plurality of minor sequences, each representing binary numbers of the series lying between respective successive numbers of the major sequence with each number of a minor sequence being spaced from a preceding number thereof by a second fixed increment.

Abstract: Charge transfer filtering and multiplexing apparatus for sampled data is described which includes a plurality of switched capacitor high pass filters coupled in parallel into the stages of a serial charge transfer shift register.

Abstract: A charge transfer shift register is described in which a first section is operated at a first clock frequency, a second section is operated at a second clock frequency, and an intermediate section located between the first and second sections is operated at fixed potential.

Abstract: An array of charge storage devices each including a pair of closely coupled conductor-insulator-semiconductor cells, one a row line connected cell and the other a column line connected cell, is provided on a common semiconductor substrate. Readout of the charges stored in a row of devices is accomplished by transferring the charge in each of the devices of the selected row of devices in one direction between the row line connected cell and the column line connected cells of a device in sequence and sensing the resultant current flow in the row line of the selected row of devices.

Abstract: An array of charge storage devices each including a pair of closely coupled conductor-insulator-semiconductor cells, one a row line connected cell and the other a column line connected cell, is provided on a common semiconductor substrate. Readout of the charges stored in each row of devices of one set of alternate rows is accomplished by transferring the charge in each of the devices of each of the rows in one direction between the row line connected cell and the column line connected cell of a device in sequence and sensing the resultant current flow in each of the row lines of the set. Readout of the charges in each row of devices of the other set of alternate rows is accomplished by transferring the charge in each of the devices of each of the rows in the other direction between the row line connected cell and the column line connected cell of a device in sequence and sensing the resultant current flow in each of the row lines of the set.

Abstract: In surface charge transfer devices a surface adjacent semiconductor layer of high resistivity and an underlying semiconductor layer of substantially lower resistivity are provided. The devices are operated to maintain depletion in the surface adjacent layer at least to the interface between the two layers to maintain substantially constant depletion depth and thereby provide substantially linear response.

Abstract: A method of making a composite conductive structure is described. The structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide covered by a layer of a silicide of the refractory metal and a layer of silicon dioxide. The method includes depositing a layer of polycrystalline silicon over the conductor and the insulating substrate, reacting the layer of polycrystalline silicon with the conductor to form a refractory metal silicide, removing the unreacted portion of the layer of polycrystalline silicon, and then oxidizing the exposed surface of the refractory metal silicide into a layer of silicon dioxide.

Abstract: A composite conductive structure in integrated circuit devices is described. The composite conductive structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide. A layer of a silicide of the refractory metal covers the conductor and a layer of silicon dioxide covers the layer of the silicide. A method of making such structures is also described.

Abstract: A solar cell which has high efficiency and which can be fabricated at low cost is described. The cell includes a semiconductor wafer with a front radiation-receiving surface which is entirely open and free of current conducting grids and also includes an array of interconnection paths which carry photocurrent from the front surface through the cell to metal electrodes on the rear surface of the cell.

Abstract: A solid state relay having a light-emitting diode, an array of series connected photodiodes and a field effect transistor is described.The light-emitting diode is optically coupled to the array of photodiodes. The conductive state of the transistor is determined entirely by the voltage developed by the array of photodiodes.

Abstract: Digital overcurrent relay apparatus utilizing sampling, digital conversion and digital comparison techniques is described. The apparatus provides a trip signal after an alternating current in a line being monitored by the apparatus exceeds a preset pick up value for a period of time which is an inverse function of the magnitude of the current expressed in multiples of pick up value.

Abstract: Digital overcurrent relay apparatus utilizing sampling, digital conversion and digital comparison techniques is described. The apparatus provides a trip signal after an alternating current in a line being monitored by the apparatus exceeds a preset pick up value for a period of time which is an inverse function of the magnitude of the current expressed in multiples of pick up value.

Abstract: An elongated body of monocrystalline semiconductor material is provided with a first region of one conductivity type entirely enclosed within a second region of the opposite conductivity type. Ohmic contacts are made to ends of the elongated body.

Abstract: An analog-to-digital converter is described in which a sequence of samples of an analog signal is converted into a sequence of binary numbers which appear at the output terminals of a composite counter comprising a first counter and a second counter. The first and second counters are gated in sequence by gating waveforms to provide for each sample the count corresponding to the logarithm of the sample. The gating waveforms are derived from a charge and discharge cycle of a capacitor to which the sample is supplied. Selected times in the charging and discharging portions of the cycle are utilized for deriving the gating waveforms.

Abstract: A conductor-insulator-semiconductor (CIS) structure for a random access surface charge memory system is disclosed. The memory system comprises an array of memory cells including charge storage regions, charge transfer regions and charge receive-source regions formed along the surface-adjacent portions of a semiconductor substrate. A charge-storage line insulatingly overlies the storage regions of a row of memory cells and a bit line, comprising an extended region of opposite-conductivity-type, interconnects the receive-source regions of the same memory cells. Addressing in the Y-direction (word selection) is provided by charge transfer lines insulatingly overlying the charge transfer regions of a column of memory cells. Selected memory cells are addressed for read and write purposes by first activating the word select line which makes available one cell in each row of the memory. The desired row is then selected by means external to the array of memory cells.

Abstract: Input structures are described for sampling an analog signal and providing charge samples in accordance therewith to charge transfer devices.