Abstract: When a processor (102) issues a request for an address (502), a determination is made as to whether or not the address is contained within a buffer (103) or cache associated with the processor (102), or the address is contained within a line of data currently being fetched from an external memory system (105). If the address is not contained within the buffer or cache and is not contained within a line being currently fetched, the current fetch will be cancelled (515, 516).

Abstract: A semiconductor device (11) has a spin on glass layer or region, and the spin on glass has a method of synthesis and use. The spin on glass composition is formed which comprises on the order of 0% to 20% by volume of tetraethylorthosilicate (TEOS), on the order of 0.01% to 20% by volume of tetraethylorthogermanate (TEOG), on the order of 0% to 1% by volume the equivalent of nitric acid (HNO.sub.3), on the order of 70% to 85% by volume of alcohol, and a remaining balance of the spin on glass composition being water. The spin on glass is applied to a semiconductor substrate and heated and/or densified to form the spin on glass layer or region.

Abstract: A method (FIGS. 6-8) for detecting and attenuating N feedback frequencies in a digitized signal uses a tree structure containing a plurality of staged filters. In a step (602), an array of digital filters (FIG. 8) having N branches (40) is constructed. The array is arranged in a tree structure with each branch (40) having several stages (42, 44, and 46). Many of the N filters are used simultaneously in multiple different branches of the tree structure thus reducing the total number of filters required to detect all N feedback frequencies. Within each branch, N-1 of the N filters are notch filters, and each of the N- 1 notch filters attenuates the digitized signal at one of the N feedback frequencies. The remaining one filter in each of the N branches is a bandpass filter that passes the remaining of the N feedback frequency. Therefore, each branch of the tree passes a unique feedback frequency absent of all other N-1 feedback frequencies.

Abstract: A method and apparatus is used to allow big-endian data and little-endian data to be read from memory in a dynamic manner. A multiplexer controller (18) is provided size bits and two low order address bits A0 and A1 as control signals from a CPU (16). A0 is used by the controller (18) to distinguish between little-endian reads and big-endian reads for both 16-bit halfword accesses and 32-bit word accesses. Using the control signals from the CPU (16), the controller (18) provides ten control signals to a multiplexer 20. One of signals A-D are enabled for byte accesses, one of signals E'-G' are enabled for big-endian halfword or word accesses, and one of the signals E"-G" are enabled for little-endian halfword or word accesses. The multiplexor switches the external data from big-endian or little-endian to a common CPU-internal format while also aligning data reads for byte and halfword accesses in response to the ten control signals.

Abstract: An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop.

Abstract: The present invention incorporates an electrically-controlled grid (250) between a liner (220) and an isolation region (252) of a processing chamber (210). The electrically-controlled grid (250) is powered during a processing step of a semiconductor substrate (230) such that particles (235) suspended in the processing chamber (212) are attracted toward the grid (250) and away from the semiconductor substrate (230). A non-adhesive liner (220) is utilized to allow particles (235) and polymers to be directed toward a pumping port (239).

Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Abstract: A chemical mechanical polishing (CMP) method utilizes a polishing pad (21) and an under pad (20). The under pad (20) has an edge portion (24) and a central portion (22). The central portion (22) has either a shore D hardness less than a shore D hardness of the portion (24), greater slurry absorption than the edge portion (24), or more compressibility than the edge portion (24). This composite material under pad (20) will improve polishing uniformity of a semiconductor wafer (39). In addition, the use of the polishing pads (20 and 21) allows for greater final wafer profile control than was previously available in the art (FIGS. 4-6).

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract: A method for chemical mechanical polishing (CMP) a copper layer (22) begins by forming the copper layer (22). The copper layer (22) is then exposed to a slurry (24). The slurry (24) contains an oxidizing agent such as H.sub.2 O.sub.2, a carboxylate salt such as ammonium citrate, an abrasive slurry such as alumna abrasive, an optional triazole or triazole derivative, and a remaining balance of a solvent such as deionized water. The use of the slurry (24) polishes the copper layer (22) with a high rate of removal whereby pitting and corrosion of the copper layer (22) is reduced and good copper interconnect planarity is achieved. This slurry (24) has good selectivity of copper to oxide, and results in copper devices which have good electrical performance. In addition, disposal of the slurry (24) is not environmentally difficult since the slurry (24) is environmentally sound when compared to other prior art slurries.

Abstract: Data processing system (800) and process (100) produce a hierarchical interconnection description of an integrated circuit design from a plurality of functional modules and a desired hierarchy. After an integrated circuit description is received (102), an interconnection structure is created (104) for each hierarchical level and functional module within the integrated circuit description. Based upon the desired hierarchy, a hierarchical tree is generated. Based upon the hierarchical tree, the interconnection structures are filled (106) with relevant interconnection and pin information to define interconnections among functional modules and hierarchical levels. After each interconnection structure is filled, a complete hierarchical interconnection description of the integrated circuit design has been completed. Finally, the hierarchical interconnection description is output (108).

Abstract: An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the embedded core are available at external terminals of the integrated circuit (10). Therefore, the wrapper speed path test cells (16 and 18) are provided. The cell (16) contains two flip-flops (20 and 22) which can be used to launch logic transitions into the embedded core (14) to perform two clock speed path testing. The cell (18) contains flip-flops (26 and 28) which can perform a speed path launch operations to a customer specified logic (12). The cell (16) can perform speed path capture operations for the customer specified logic (12) whereas the cell (18) can perform speed path capture operations for the embedded core (14).

Abstract: An EEPROM cell (32) is formed having a vertical select gate (34) and a horizontal select gate (40). The vertical select gate (34) and the horizontal select gate (40) enable two dimensional decoding which selects which one or which plurality of memory cells (32) are enabled for program, erase and read operations. An additional select gate having a control electrode (44) can be added to the cell (32) to provide additional decoding as is necessary. This split gate EEPROM cell (32) can be readily integrated onto an integrated circuit which also contains flash memory (204). The flash memory (204) and the split control gate EEPROM array (202) can share the same common charge pumps circuit (208).

Abstract: A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file (FIG. 2) in memory (24). The trace file is then scanned using a window size greater than two (i.e., more than two instructions or basic blocks/ groups of instructions are selected as each window) and correlations are determined between several pairs of instructions in each window (FIGS. 9 and 10). The correlations obtained by the window procedure are then analyzed (FIG. 11) to determine an efficient ordering of computer instructions for subsequent execution by any target CPU.

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).

Abstract: A method and apparatus for performing block encoding in an asymmetrical digital subscriber line (ADSL) system uses a pipelined structure. The parity check circuit (116) contains a plurality of pipeline stages (201, 203, 205, and 207). Each stage contains an ADSL input data register (200, 202, 204, and 206) at a beginning of each stage and a carry register (208, 210, and 212) separating each stage. Each stage contains a plurality of carry circuits (214-220) which are serially coupled together by carry signals. The plurality of carry circuits (214-220) use generator polynomial root (.alpha.) processing involving serial carry propagation whereby the pipelining is implemented in the stages (201, 203, 205, and 207) in order to break the serial carry path from one long string to smaller segmented strings which are pipelined together. This pipelining is performed so that parity generation can occur at the higher frequencies required by ADSL systems.

Abstract: A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode (126), and a gate electrode (114). A second N-type transistor, which is a word-line select transistor (504), has a first current electrode (101), a second current electrode (128), and a gate electrode (116). A P-channel pull up transistor (502) has a first current electrode (103), a second current electrode (124), and a gate electrode (114). The coupling of the electrodes (101 and 103) form a storage node of the one half of the memory cell which is contacted electrically by a conductive contact (140).

Abstract: An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

Abstract: A method and apparatus for allowing the soft defect detection testing (SDDT) of an memory array (106) of a data processor (100) begins by providing a control value to a memory controller (111). The control value determines whether a switching circuit (104) will apply a VDD power supply voltage from a VDD terminal (132) or a Vstby power supply voltage from a Vstby terminal (130) to a selected portion of the memory array (106). When in an SDDT test mode, the selected portion of the memory array (106) is supplied by the Vstby terminal (130). While being supplied by the Vstby terminal (130), the selected portion of the memory array (106) is SDDT tested by coupling a current detection device to the pin (130) and measuring a current I drawn by the selected portion of the memory array (106).