Abstract: An electronic component (15) such as a printed circuit board (PCB) is formed using a sintering process. A layer of dielectric powder (11) is partially converted to a solid layer of dielectric material (14) by exposing selective portions of the powder (11) to a laser (17). A layer of conductive powder (20) is then formed over the solid layer of dielectric material (14) and selectively sintered to form a solid layer of conductive material (19). This process can be used to form an interconnect structure (45), a coaxial structure (60), a cavity (89), a trench structure (90), or a slug (91), conductive traces (19), bond pads (31), or any other circuit board structure.

Abstract: Circuitry (20) and an associated an method of operation provides system data (30) and scan data (32) to a latch portion (42) of a data storage element in a reduced setup time period. For each data storage element, a system data transfer gate (22) provides system data (30) to a master latch portion (42) while a scan data transfer gate (24) provides scan data (32) to the master latch portion (42). The scan data (24) and system data transfer (22) gates minimize the set-up time required for data entering the data storage element. Scan chains incorporating the data storage elements include scan data input ports and scan data output ports as well as connections between data storage elements in an associated scan chain. A controller (26) operated by a scan enable signal (38) and a system clock (40) provide control signals to the system data transfer gate (22) and the scan data transfer gate (24) to cause the gates to selectively pass data.

Abstract: The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.

Abstract: A method (FIGS. 5-6) and a structure (FIGS. 3-4) are taught herein for prioritizing and transmitting forward monitoring cells (FMCs) for performance monitoring in an asynchronous transfer mode (ATM) system. An ATM system may have multiple physical lines which have many virtual paths which have multiple virtual connections. These paths/connections may be performance monitored by transmitting an FMC each time N ATM data cells are received for the connection/path (wherein N is number which may be different for each connection/path). The number of data cells are stored via a counter for each connection/path being monitored. Once N ATM cells are received on a given connection/path, an FMC descriptor is queued which indicates that the FMC cell for the given connection/path must be transmitted before receipt of N/2 subsequent cells received by the given connection/path. A priority (which is a function of one of the counters) is used to ensure that the N/2 requirement is satisfied.

Abstract: A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.

Abstract: A test structure and test methodology are taught herein wherein a test structure (10) is used to test an entire integrated circuit product wafer (44). The test structure (10) has a backing support wafer (39). A die attach compound (38) is used to attach a plurality of segmented individual test integrated circuits 28-34 to the backing support wafer (39). The plurality of test integrated circuits 28-34 have a top conductive bump layer (26). This conductive bump layer (26) is contacted to a thin film signal distribution layer (14) which contains conductive interconnects, conductive layers, and dielectric layers which route electrical signals as illustrated in FIG. 2 . The layer 14 also conductively connects to bumps (46) on a product wafer (44). In addition, leads (40) are coupled to conductive elements of the layer (14).

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Abstract: A method for removing particles (21-24) begins by providing a substrate (10). The substrate (10) contains one or more integrated circuit layers (12) having a top surface (12A). The particles (21-24) are in contact with top surface (12A). A tape (14) comprising an adhesion layer (16) and a carrier film (18) is applied to the surface (12A) such that the adhesion layer (16) is in contact with the particles (21-24). The tape (14) is then removed from the surface (12A) wherein the adhesion layer (16) is able to remove the particles (21-24) from the surface (12A) of the substrate (10). The tape (14) can be applied to a front or active surface of a semiconductor wafer, where the surface either has a topography containing high areas (37) and low areas (39) or has a planarized surface (12A) in order to reduce a total number of particles (21-24) on the surface (12A).

Abstract: A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.

Abstract: A method and apparatus for providing low power management of a data processing system (FIG. 1) involves a CPU (12) communicating to a register file (16) in a processor (10). The CPU (12) communicates low power control and status values to/from the register file (16) via internal register file buses that are separate from internal data busses and address buses (22-26) which communicate with external data busses and address buses (34-38). The low power control and status values are stored in internal register (16a and 16b) which are coupled directly to external pins (52 and 54) of the processor (10). The registers (16a and 16b) are part of the user programming model of the processor (10). The low power information communicated between CPU (16), register (16a and 16b) and the pins (52 and 54) is communicated with little or no bandwidth problems and is efficient due to the separation from buses (22-26).

Abstract: The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable.

Abstract: The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shifting transistors (16), a plurality of bit reversal transistors (20), control lines (18) and (22) for each, and a controller (24). The plurality of shifting transistors (16) operably couple the input lines (12) to the output lines (14) such that the controller (24) may selectively operate the shifting transistors (22) to produce shifted outputs of the input data D.sub.0 through D.sub.3 on the output lines (14). The controller (24) selectively operates the bit reversal transistors (20) to produce a bit reversed representation of the input data on the output lines (14). Precharge circuit (30) precharges the output lines (14) so that they may be statically driven. The circuit (10) may include multiplexors (25), (26), and (27) to enable arithmetic shifts.

Abstract: An apparatus and method for laser ablating residue off of probe tips. In one embodiment, the probe tips of the probe needles (16) contact the test pads of an integrated circuit on a wafer (18). The probe tips build up a residue over time. This residue is due to the probe tips coming into contact with integrated circuit wafer layers such as layers (114), (120), (122), (124), and (126). This residue can be vaporized from the surface of the probe needles via exposure to a laser light. The probe needles (16) are exposed to a laser light created by a laser source (28) and ported to the probe tips by a fiber optic cable (26).

Abstract: A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

Abstract: A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.

Abstract: A method of packaging a semiconductor device includes providing a chase (11) with a cavity (12). The cavity (12) has a cavity sidewall (13). A substrate (19) is provided having a substrate sidewall (20) wherein the substrate (19) is positioned in the cavity (12). A space or gap (21) is formed between the substrate sidewall (20) and the cavity sidewall (13). To insulate the gap (21) from mold compound (27), a barrier layer (22) is placed adjacent to the chase (11) and adjacent to the substrate (19) wherein the barrier layer (22) overlays a portion of the space or gap (21). Mold compound (27) is injected over the barrier layer (22), over the portion of the space or gap (21), and toward the substrate (19). The barrier layer (22) is used to prohibit the mold compound (27) from contacting the substrate sidewall (20) and the cavity sidewall (13) when the substrate (19) is being encapsulated.

Abstract: A fiber data distributed interface (FDDI) system uses an MLT3A encoding scheme in order to reduce DC bias or baseline wander. The MLT3A encoding scheme is a scheme wherein logical zeros are transmitted as ground voltages and logical ones are transmitted as one of either positive voltages or negative voltages depending upon past transmission history (FIG. 4 ) wherein the past history is recorded by a counter C or an analog circuit. MLT3A ensures that the baseline wander or DC bias returns to zero or is maintained as close to zero as possible in a timely manner so that no FDDI systems will fail from baseline wander.

Abstract: This application is dedicated to the public. A method and apparatus for reducing the emissions of a fluorinated gas from a wafer processing facility begins by providing a fluorinated exhaust gas from wafer processing tools (10) through (16) via an input line (17). The fluorinated exhaust gas is then optionally gettered via an gettering system (18) to remove oxygen from the exhaust gas. After gettering, the fluorinated exhaust gas is directed to a molten aluminum bath (44). The fluorine in the exhaust gas reacts with the aluminum to form AlF.sub.3. A measurement device (56) is used to monitor the amount of fluorine being exhausted from the molten aluminum bath (44). When the amount of fluorine in the exhaust is too high, the molten aluminum bath (44) is saturated with fluorine. The bath is then cooled to form an inert solid brick of AlF.sub.3. Therefore, fluorinated gases which are detrimental to the environment are cost-effectively removed from the output of a wafer fabrication facility.